234 research outputs found
Doctor of Philosophy
dissertationFormal verification of hardware designs has become an essential component of the overall system design flow. The designs are generally modeled as finite state machines, on which property and equivalence checking problems are solved for verification. Reachability analysis forms the core of these techniques. However, increasing size and complexity of the circuits causes the state explosion problem. Abstraction is the key to tackling the scalability challenges. This dissertation presents new techniques for word-level abstraction with applications in sequential design verification. By bundling together k bit-level state-variables into one word-level constraint expression, the state-space is construed as solutions (variety) to a set of polynomial constraints (ideal), modeled over the finite (Galois) field of 2^k elements. Subsequently, techniques from algebraic geometry -- notably, Groebner basis theory and technology -- are researched to perform reachability analysis and verification of sequential circuits. This approach adds a "word-level dimension" to state-space abstraction and verification to make the process more efficient. While algebraic geometry provides powerful abstraction and reasoning capabilities, the algorithms exhibit high computational complexity. In the dissertation, we show that by analyzing the constraints, it is possible to obtain more insights about the polynomial ideals, which can be exploited to overcome the complexity. Using our algorithm design and implementations, we demonstrate how to perform reachability analysis of finite-state machines purely at the word level. Using this concept, we perform scalable verification of sequential arithmetic circuits. As contemporary approaches make use of resolution proofs and unsatisfiable cores for state-space abstraction, we introduce the algebraic geometry analog of unsatisfiable cores, and present algorithms to extract and refine unsatisfiable cores of polynomial ideals. Experiments are performed to demonstrate the efficacy of our approaches
Applying Formal Methods to Networking: Theory, Techniques and Applications
Despite its great importance, modern network infrastructure is remarkable for
the lack of rigor in its engineering. The Internet which began as a research
experiment was never designed to handle the users and applications it hosts
today. The lack of formalization of the Internet architecture meant limited
abstractions and modularity, especially for the control and management planes,
thus requiring for every new need a new protocol built from scratch. This led
to an unwieldy ossified Internet architecture resistant to any attempts at
formal verification, and an Internet culture where expediency and pragmatism
are favored over formal correctness. Fortunately, recent work in the space of
clean slate Internet design---especially, the software defined networking (SDN)
paradigm---offers the Internet community another chance to develop the right
kind of architecture and abstractions. This has also led to a great resurgence
in interest of applying formal methods to specification, verification, and
synthesis of networking protocols and applications. In this paper, we present a
self-contained tutorial of the formidable amount of work that has been done in
formal methods, and present a survey of its applications to networking.Comment: 30 pages, submitted to IEEE Communications Surveys and Tutorial
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Using formal methods to support testing
Formal methods and testing are two important approaches that assist in the development of high quality software. While traditionally these approaches have been seen as rivals, in recent
years a new consensus has developed in which they are seen as complementary. This article reviews the state of the art regarding ways in which the presence of a formal specification can be used to assist testing
Soft Error Analysis and Mitigation at High Abstraction Levels
Radiation-induced soft errors, as one of the major reliability challenges in future technology nodes, have to be carefully taken into consideration in the design space exploration. This thesis presents several novel and efficient techniques for soft error evaluation and mitigation at high abstract levels, i.e. from register transfer level up to behavioral algorithmic level. The effectiveness of proposed techniques is demonstrated with extensive synthesis experiments
Hardware synthesis from high-level scenario specifications
PhD ThesisThe behaviour of many systems can be partitioned into scenarios. These facilitate
engineers’ understanding of the specifications, and can be composed into efficient
implementations via a form of high-level synthesis. In this work, we focus on highly
concurrent systems, whose scenarios are typically described using concurrency models
such as partial orders, Petri nets and data-flow structures.
In this thesis, we study different aspects of hardware synthesis from high-level
scenario specifications. We propose new formal models to simplify the specification
of concurrent systems, and algorithms for hardware synthesis and verification of the
scenario-based models of such systems. We also propose solutions for mapping scenariobased
systems on silicon and evaluate their efficiency.
Our experiments show that the proposed approaches improve the design of concurrent
systems. The new formalisms can break down complex specifications into
significantly simpler scenarios automatically, and can be used to fully model the dataflow
of operations of reconfigurable event-driven systems. The proposed heuristics for
mapping the scenarios of a system to a digital circuit supports encoding constraints,
unlike existing methods, and can cope with specifications comprising hundreds of
scenarios at the cost of only 5% of area overhead compared to exact algorithms.
These experiments are driven by three case studies: (1) hardware synthesis of control
architectures, e.g. microprocessor control units; (2) acceleration of the ordinal pattern
encoding, i.e. an algorithm for detecting repetitive patterns within data streams; (3) and
acceleration of computational drug discovery, i.e. computation of shortest paths in large
protein-interaction networks.
Our findings are employed to design two prototypes, which have a practical value for
the considered case studies. The ordinal pattern encoding accelerator is asynchronous,
highly resilient to unstable voltage supply, and designed to perform a range of computations
via runtime reconfiguration. The drug discovery accelerator is synchronous, and
up to three orders of magnitude faster than conventional software implementations
Model Checking and Model-Based Testing : Improving Their Feasibility by Lazy Techniques, Parallelization, and Other Optimizations
This thesis focuses on the lightweight formal method of model-based testing for checking safety properties, and derives a new and more feasible approach.
For liveness properties, dynamic testing is impossible, so feasibility is increased by specializing on an important class of properties, livelock freedom, and deriving a more feasible model checking algorithm for it.
All mentioned improvements are substantiated by experiments
Computer Aided Verification
This open access two-volume set LNCS 13371 and 13372 constitutes the refereed proceedings of the 34rd International Conference on Computer Aided Verification, CAV 2022, which was held in Haifa, Israel, in August 2022. The 40 full papers presented together with 9 tool papers and 2 case studies were carefully reviewed and selected from 209 submissions. The papers were organized in the following topical sections: Part I: Invited papers; formal methods for probabilistic programs; formal methods for neural networks; software Verification and model checking; hyperproperties and security; formal methods for hardware, cyber-physical, and hybrid systems. Part II: Probabilistic techniques; automata and logic; deductive verification and decision procedures; machine learning; synthesis and concurrency. This is an open access book
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