A built-in self-test technique for high speed analog-to-digital converters

Fundação para a Ciência e a Tecnologia (FCT) - PhD grant (SFRH/BD/62568/2009

Design of Energy-Efficient A/D Converters with Partial Embedded Equalization for High-Speed Wireline Receiver Applications

As the data rates of wireline communication links increases, channel impairments such as skin effect, dielectric loss, fiber dispersion, reflections and cross-talk become more pronounced. This warrants more interest in analog-to-digital converter (ADC)-based serial link receivers, as they allow for more complex and flexible back-end digital signal processing (DSP) relative to binary or mixed-signal receivers. Utilizing this back-end DSP allows for complex digital equalization and more bandwidth-efficient modulation schemes, while also displaying reduced process/voltage/temperature (PVT) sensitivity. Furthermore, these architectures offer straightforward design translation and can directly leverage the area and power scaling offered by new CMOS technology nodes. However, the power consumption of the ADC front-end and subsequent digital signal processing is a major issue. Embedding partial equalization inside the front-end ADC can potentially result in lowering the complexity of back-end DSP and/or decreasing the ADC resolution requirement, which results in a more energy-effcient receiver. This dissertation presents efficient implementations for multi-GS/s time-interleaved ADCs with partial embedded equalization. First prototype details a 6b 1.6GS/s ADC with a novel embedded redundant-cycle 1-tap DFE structure in 90nm CMOS. The other two prototypes explain more complex 6b 10GS/s ADCs with efficiently embedded feed-forward equalization (FFE) and decision feedback equalization (DFE) in 65nm CMOS. Leveraging a time-interleaved successive approximation ADC architecture, new structures for embedded DFE and FFE are proposed with low power/area overhead. Measurement results over FR4 channels verify the effectiveness of proposed embedded equalization schemes. The comparison of fabricated prototypes against state-of-the-art general-purpose ADCs at similar speed/resolution range shows comparable performances, while the proposed architectures include embedded equalization as well

DESIGN OF A BURST MODE ULTRA HIGH-SPEED LOW-NOISE CMOS IMAGE SENSOR

Ultra-high-speed (UHS) image sensors are of interest for studying fast scientific phenomena and may also be useful in medicine. Several published studies have recently achieved frame rates of up to millions of frames per second (Mfps) using advanced processes and/or customized processes. This thesis presents a burst-mode (108 frames) UHS low-noise CMOS image sensor (CIS) based on charge-sweep transfer gates in an unmodified, standard 180 nm front-side-illuminated CIS process. By optimizing the photodiode geometry, the 52.8 μm pitch pixels with 20x20 μm^2 of active area, achieve a charge-transfer time of less than 10 ns. A proof-of-concept CIS was designed and fabricated. Through characterization, it is shown that the designed CIS has the potential to achieve 20 Mfps with an input-referred noise of 5.1 e− rms

Concepts for smart AD and DA converters

This thesis studies the `smart' concept for application to analog-to-digital and digital-to-analog converters. The smart concept aims at improving performance - in a wide sense - of AD/DA converters by adding on-chip intelligence to extract imperfections and to correct for them. As the smart concept can correct for certain imperfections, it can also enable the use of more efficient architectures, thus yielding an additional performance boost. Chapter 2 studies trends and expectations in converter design with respect to applications, circuit design and technology evolution. Problems and opportunities are identfied, and an overview of performance criteria is given. Chapter 3 introduces the smart concept that takes advantage of the expected opportunities (described in chapter 2) in order to solve the anticipated problems. Chapter 4 applies the smart concept to digital-to-analog converters. In the discussed example, the concept is applied to reduce the area of the analog core of a current-steering DAC. It is shown that a sub-binary variable-radix approach reduces the area of the current-source elements substantially (10x compared to state-of-the-art), while maintaining accuracy by a self-measurement and digital pre-correction scheme. Chapter 5 describes the chip implementation of the sub-binary variable-radix DAC and discusses the experimental results. The results confirm that the sub-binary variable-radix design can achieve the smallest published current-source-array area for the given accuracy (12bit). Chapter 6 applies the smart concept to analog-to-digital converters, with as main goal the improvement of the overall performance in terms of a widely used figure-of-merit. Open-loop circuitry and time interleaving are shown to be key to achieve high-speed low-power solutions. It is suggested to apply a smart approach to reduce the effect of the imperfections, unintentionally caused by these key factors. On high-level, a global picture of the smart solution is proposed that can solve the problems while still maintaining power-efficiency. Chapter 7 deals with the design of a 500MSps open-loop track-and-hold circuit. This circuit is used as a test case to demonstrate the proposed smart approaches. Experimental results are presented and compared against prior art. Though there are several limitations in the design and the measurement setup, the measured performance is comparable to existing state-of-the-art. Chapter 8 introduces the first calibration method that counteracts the accuracy issues of the open-loop track-and-hold. A description of the method is given, and the implementation of the detection algorithm and correction circuitry is discussed. The chapter concludes with experimental measurement results. Chapter 9 introduces the second calibration method that targets the accuracy issues of time-interleaved circuits, in this case a 2-channel version of the implemented track-and-hold. The detection method, processing algorithm and correction circuitry are analyzed and their implementation is explained. Experimental results verify the usefulness of the method

Development and Performance of Kyoto's X-ray Astronomical SOI pixel (SOIPIX) sensor

We have been developing monolithic active pixel sensors, known as Kyoto's X-ray SOIPIXs, based on the CMOS SOI (silicon-on-insulator) technology for next-generation X-ray astronomy satellites. The event trigger output function implemented in each pixel offers microsecond time resolution and enables reduction of the non-X-ray background that dominates the high X-ray energy band above 5--10 keV. A fully depleted SOI with a thick depletion layer and back illumination offers wide band coverage of 0.3--40 keV. Here, we report recent progress in the X-ray SOIPIX development. In this study, we achieved an energy resolution of 300~eV (FWHM) at 6~keV and a read-out noise of 33~e- (rms) in the frame readout mode, which allows us to clearly resolve Mn-K$\alpha$ and K$\beta$. Moreover, we produced a fully depleted layer with a thickness of $500~{\rm \mu m}$. The event-driven readout mode has already been successfully demonstrated.Comment: 7pages, 12figures, SPIE Astronomical Telescopes and Instrumentation 2014, Montreal, Quebec, Canada. appears as Proc. SPIE 9147, Space Telescopes and Instrumentation 2014: Ultraviolet to Gamma Ra

Low power CMOS vision sensor for foreground segmentation

This thesis focuses on the design of a top-ranked algorithm for background subtraction, the Pixel Adaptive Based Segmenter (PBAS), for its mapping onto a CMOS vision sensor on the focal plane processing. The redesign of PBAS into its hardware oriented version, HO-PBAS, has led to a less number of memories per pixel, along with a simpler overall model, yet, resulting in an acceptable loss of accuracy with respect to its counterpart on CPU. This thesis features two CMOS vision sensors. The first one, HOPBAS1K, has laid out a 24 x 56 pixel array onto a miniasic chip in standard 180 nm CMOS technology. The second one, HOPBAS10K, features an array of 98 x 98 pixels in standard 180 nm CMOS technology too. The second chip fixes some issues found in the first chip, and provides good hardware and background performance metrics

Design of Power/Analog/Digital Systems Through Mixed-Level Simulations

In recent years the development of the applications in the field of telecommunications, data processing, control, renewable energy generation, consumer and automotive electronics determined the need for increasingly complex systems, also in shorter time to meet the growing market demand. The increasing complexity is mainly due to the mixed nature of these systems that must be developed to accommodate the new functionalities and to satisfy the more stringent performance requirements of the emerging applications. This means a more complex design and verification process. The key to managing the increased design complexity is a structured and integrated design methodology which allows the sharing of different circuit implementations that can be at transistor level and/or at a higher level (i.e.HDL languages).In order to expedite the mixed systems design process it is necessary to provide: an integrated design methodology; a suitable supporting tool able to manage the entire design process and design complexity and its successive verification.It is essential that the different system blocks (power, analog, digital), described at different level of abstraction, can be co-simulated in the same design context. This capability is referred to as mixed-level simulation.One of the objectives of this research is to design a mixed system application referred to the control of a coupled step-up dc-dc converter. This latter consists of a power stage designed at transistor-level, also including accurate power device models, and the analog controller implemented using VerilogA modules. Digital controllers are becoming very attractive in dc-dc converters for their programmability, ability to implement sophisticated control schemes, and ease of integration with other digital systems. Thus, in this dissertation it will be presented a detailed design of a Flash Analog-to-Digital Converter (ADC). The designed ADC provides medium-high resolution associated to high-speed performance. This makes it useful not only for the control application aforementioned but also for applications with huge requirements in terms of speed and signal bandwidth. The entire design flow of the overall system has been conducted in the Cadence Design Environment that also provides the ability to mixed-level simulations. Furthermore, the technology process used for the ADC design is the IHP BiCMOS 0.25 µm by using 50 GHz NPN HBT devices

Integration and evaluation of a near-infrared camera utilizing a HgCdTe NICMOS3 array for the Mt. Palomar 200-inch Observatory

In this paper we describe the main subsystems that constitute the Mt. Palomar Prime Focus InfraRed Camera (PFIRCAM), together with some of the characterization data obtained for the focal plane array. This camera is currently a facility instrument at the 200-inch Mt. Palomar Observatory. It helps to satisfy the observational needs of astronomers in the spectral range of 1 micrometers to 2.5 micrometers by utilizing a HgCdTe NICMOS3 array. The camera has a plate scale of 0.54 arcsec/pixel for an overall FOV of 138 X 138 arcsec

Fundamental Blocks for a 0.18um Cyclic Analog-to-Digital Converter

The goal of this project was to design a fully differential Cyclic Analog-to-Digital Converter, and test the functionality of its major blocks. The converter is an integrated circuit designed for the CMOS 0.18 micron fabrication process. It is self-calibrating and performs 1 million samples per second. Design techniques used include switched capacitor networks, differential amplifier, replica biasing, and calibration in the off-chip digital domain. The project is sponsored by the New England Center for Analog and Mixed Signal Design (NECAMSID)