Design of sigma-delta modulators for analog-to-digital conversion intensively using passive circuits

This thesis presents the analysis, design implementation and experimental evaluation of passiveactive discrete-time and continuous-time Sigma-Delta (ΣΔ) modulators (ΣΔMs) analog-todigital converters (ADCs). Two prototype circuits were manufactured. The first one, a discrete-time 2nd-order ΣΔM, was designed in a 130 nm CMOS technology. This prototype confirmed the validity of the ultra incomplete settling (UIS) concept used for implementing the passive integrators. This circuit, clocked at 100 MHz and consuming 298 μW, achieves DR/SNR/SNDR of 78.2/73.9/72.8 dB, respectively, for a signal bandwidth of 300 kHz. This results in a Walden FoMW of 139.3 fJ/conv.-step and Schreier FoMS of 168 dB. The final prototype circuit is a highly area and power efficient ΣΔM using a combination of a cascaded topology, a continuous-time RC loop filter and switched-capacitor feedback paths. The modulator requires only two low gain stages that are based on differential pairs. A systematic design methodology based on genetic algorithm, was used, which allowed decreasing the circuit’s sensitivity to the circuit components’ variations. This continuous-time, 2-1 MASH ΣΔM has been designed in a 65 nm CMOS technology and it occupies an area of just 0.027 mm2. Measurement results show that this modulator achieves a peak SNR/SNDR of 76/72.2 dB and DR of 77dB for an input signal bandwidth of 10 MHz, while dissipating 1.57 mW from a 1 V power supply voltage. The ΣΔM achieves a Walden FoMW of 23.6 fJ/level and a Schreier FoMS of 175 dB. The innovations proposed in this circuit result, both, in the reduction of the power consumption and of the chip size. To the best of the author’s knowledge the circuit achieves the lowest Walden FOMW for ΣΔMs operating at signal bandwidth from 5 MHz to 50 MHz reported to date

Implementation of a sigma delta modulator for a class D audio power amplifier

Dissertação para obtenção do Grau de Mestre em Engenharia Electrotécnica e de Computadore

A CMOS Digital Beamforming Receiver

As the demand for high speed communication is increasing, emerging wireless techniques seek to utilize unoccupied frequency ranges, such as the mm-wave range. Due to high path loss for higher carrier frequencies, beamforming is an essential technology for mm-wave communication. Compared to analog beamforming, digital beamforming provides multiple simultaneous beams without an SNR penalty, is more accurate, enables faster steering, and provides full access to each element. Despite these advantages, digital beamforming has been limited by high power consumption, large die area, and the need for large numbers of analog-to-digital converters. Furthermore, beam squinting errors and ADC non-linearity limit the use of large digital beamforming arrays. We address these limitations. First, we address the power and area challenge by combining Interleaved Bit Stream Processing (IL-BSP) with power and area efficient Continuous-Time Band-Pass Delta-Sigma Modulators (CTBPDSMs). Compared to conventional DSP, IL-BSP reduces both power and area by 80%. Furthermore, the new CTBPDSM architecture reduces ADC area by 67% and the energy per conversion by 43% compared to previous work. Second, we introduce the first integrated digital true-time-delay digital beamforming receiver to resolve the beam squinting. True-time-delay beamforming eliminates squinting, making it an ideal choice for large-array wide-bandwidth applications. Third, we present a new current-steering DAC architecture that provides a constant output impedance to improve ADC linearity. This significantly reduces distortion, leading to an SFDR improvement of 13.7 dB from the array. Finally, we provide analysis to show that the ADC power consumption of a digital beamformer is comparable to that of the ADC power for an analog beamformer. To summarize, we present a prototype phased array and a prototype timed array, both with 16 elements, 4 independent beams, a 1 GHz center frequency, and a 100 MHz bandwidth. Both the phased array and timed array achieve nearly ideal conventional and adaptive beam patterns, including beam tapering and adaptive nulling. With an 11.2 dB array gain, the phased array achieves a 58.5 dB SNDR over a 100 MHz bandwidth, while consuming 312 mW and occupying 0.22 mm2. The timed array achieves an EVM better than -37 dB for 5 MBd QAM-256 and QAM-512, occupies only 0.29 mm2, and consumes 453 mW.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/147716/1/smjang_1.pd

Design of a Comparator and an Amplifier in CMOS using standard logic gates

Using standard logic gates in CMOS, or standard-cells, has the advantage of full synthe- sizability, as well as the voltage scalability between technologies. In this work a general pur- pose standard-cell-based voltage comparator and amplifier are presented. The objective is to design a general purpose standard-cell-based comparator and ampli- fier in 130 nm CMOS by optimizing the already existing topologies with the aim of improving some of the specifications of the studied topologies. Various simulation testbenches were made to test the studied topologies of comparators and amplifiers, in which the results were compared. The top performing standard-cell com- parator and amplifier were then modified. After successfully designing the comparator, it was used in the design of an opamp-less Sigma-Delta modulator (ΣΔM). The proposed comparator is an OR-AND-Inverter-based comparator with dual inputs and outputs, achieving a delay of 109 ps, static input offset of 591 μV, and random offset of 10.42 μV, while dissipating 890 μW, when clocked at 1.5 GHz. The proposed amplifier is a single-path three-stage inverter-based operational transcon- ductance amplifier (OTA) with active common-mode feedback loop, achieving a DC gain of 63 dB, 1444 MHz of unity-gain bandwidth, 51º of phase margin while dissipating 1098 μW, considering a load of 1 pF. The proposed comparator was employed in the ΣΔM with a standard-cell based edge- triggered flip-flop. The ΣΔM, with a sampling frequency of 2 MHz and a signal bandwidth of 2.5 kHz, achieved a peak SNDR of 69 dB while dissipating only 136.7 μW.Utilizando portas lógicas básicas em CMOS oferece a vantagem de um circuito comple- tamente sintetizável, tal como o escalamento de tensão entre tecnologias. Neste trabalho são apresentados um comparador de tensão e um amplificador utilizando portas lógicas. O objetivo deste trabalho é desenhar um comparador e um amplificador utilizando por- tas lógicas através do estudo e otimização de topologias já existentes com a finalidade de me- lhoramento de algumas das especificações das mesmas. Foram realizados vários bancos de teste para testar as topologias estudadas de compa- radores e amplificadores, em que os resultados foram comparados. As topologias de compa- radores e amplificadores de portas lógicas com melhor performance foram então modificadas. Após o comparador ter sido projetado com sucesso, foi utilizado na projeção de um modula- dor Sigma-Delta (ΣΔM) opamp-less. O comparador proposto é um OR-AND-Inversor com duas entradas e saídas, que apre- senta um atraso de 109 ps, offset estático na entrada de 591 μV, offset aleatório de 10.42 μV, enquanto dissipando 890 μW, utilizando uma frequência de relógio de 1.5 GHz O amplificador proposto é um amplificador operacional de transcondutância single- path three-stage inverter-based com um loop ativo de realimentação do modo-comum, que apresenta um ganho DC de 63 dB, 1444 MHz de ganho-unitário de largura de banda, 51º de margem de fase e dissipando 1098 μW, considerando uma carga de 1 pF. O comparador proposto foi aplicado no ΣΔM com um flip-flop edge-triggered baseado em portas lógicas. O ΣΔM, com uma frequência de amostragem de 2 MHz e uma largura de banda de 2.5 kHz, apresentou um SNDR máximo de 69 dB enquanto dissipando apenas 136.7 μW

Wide-bandwidth, high-resolution delta-sigma analog-to-digital converters

There is a significant need in recent mobile communication and wireless broadband systems for high-performance analog-to-digital converters (ADCs) that have wide bandwidth (BW>5-MHz) and high data rate (>100-Mbps). A delta-sigma ADC is recognized as a power-efficient ADC architecture when high resolution (>12-b) is required. This is due to several advantages of the delta-sigma ADC including relaxed anti-aliasing filter requirements, high signal-to-noise and distortion ratio (SNDR) and most importantly, reduced sensitivity to analog imperfections. In this thesis, several structures and design techniques are developed for the implementation of continuoustime (CT) and discrete-time (DT) delta-sigma ADCs. These techniques save the total power consumption, reduce the design complexity, and decrease the chip die area of delta-sigma modulators. First a 4th-order single stage CT delta-sigma ADC with a novel single-amplifier-biquad (SAB) based loop filter is presented. By utilizing the SAB networks in the loop filter of an Nth-order CT delta-sigma modulator, it requires only half the number of active amplifiers and feed-forward branches used in the conventional modulator architecture, thus decreasing the power consumption and area by reducing the number of amplifiers. The proposed scheme also enables the modulator to use a switch-capacitor (SC) adder due to the reduced number of feedforward branches to its summing block. As a sequence, it consumes less power compared to a conventional CT adder. With a 130-nm CMOS technology, the fabricated prototype IC achieves a dynamic range of 80 dB with 10 MHz signal bandwidth and analog power dissipation lower than 12 mW. Presented as the second scheme to save power consumption and chip die area in ΔΣ modulators is a new stage-sharing technique in a discrete-time 2-2 MASH ΔΣ ADC. The proposed technique shares all the active blocks of the modulator second stage with its first stage during the two non-overlapping clock phases. Measurement results show that the modulator designed in a 0.13-um CMOS technology achieves 76 dB SNDR over a 10 MHz conversion bandwidth dissipating less than 9 mW analog power

A Continuous-Time Delta-Sigma Modulator for Ultra-Low-Power Radios

The increasing need of digital signal processing for telecommunication and multimedia applications, implemented in complementary metal-oxide semiconductor (CMOS) technology, creates the necessity for high-resolution analog-to-digital converters (ADCs). Based on the sampling frequency, ADCs are of two types: Nyquist-rate converters and oversampling converters. Oversampling converters are preferred for low-bandwidth applications such as audio and instrumentation because they provide inherently high resolution when coupled with proper noise shaping. This allows to push noise out of signal band, thus increasing the signal-to-noise ratio (SNR). Continuous time delta-sigma ADCs are becoming more popular than discrete-time ADCs primarily because of inherent anti-aliasing filtering, reduced settling time and low-power consumption. In this thesis, a 2nd-order 4-bits continuous-time (CT) delta-sigma modulator (DSM) for radio applications is designed. It employs a 2nd-order loop filter with a single operational amplifier. Implemented in a 65-nanometer CMOS technology, the modulator runs on a 0.8-V supply and achieves a SNR of 70dB over a 500-kHz signal bandwidth. The modulator operates with an oversampling ratio (OSR) of 16 and a sampling frequency of 16MHz. In the first chapter the principles of ΔΣ modulators are analysed, introducing the differences between discrete-time (DT) modulators and continuous-time (CT) modulators. In the next chapter the techniques to design a ΔΣ modulators for ultra-low-power radios are presented. The third chapter talks over the design of the operational amplifier, which appears inside the loop filter. In the fourth chapter the performance of the complete ΔΣ modulator, which employs a flash quantizer, is shown. Finally, in the last chapter, a performance analysis is carried out replacing the flash quantizer with an asynchronous SAR quantizer. The analysis shows that a further reduction of the quantizer power consumption of about 40% is possible. The conjunction of this replacement with the power-saving technique implemented in the loop filter appears relevant

System Design of a Wide Bandwidth Continuous-Time Sigma-Delta Modulator

Sigma-delta analog-to-digital converters are gaining in popularity in recent times because of their ability to trade-off resolutions in the time and voltage domains. In particular, continuous-time modulators are finding more acceptance at higher bandwidths due to the additional advantages they provide, such as better power efficiency and inherent anti-aliasing filtering, compared to their discrete-time counterparts. This thesis work presents the system level design of a continuous-time low-pass sigma-delta modulator targeting 11 bits of resolution over 100MHz signal bandwidth. The design considerations and tradeoffs involved at the system level are presented. The individual building blocks in the modulators are modeled with non-idealities and specifications for the various blocks are obtained in detail. Simulation results obtained from behavioral models of the system in MATLAB and Cadence environment show that a signal-to-noise-and-distortion-ratio (SNDR) of 69.6dB is achieved. A loop filter composed of passive LC sections is utilized in place of integrators or resonators used in traditional modulator implementations. Gain in the forward signal path is realized using active circuits based on simple transconductance stages. A novel method to compensate for excess delay in the loop without using an extra summing amplifier is proposed

Design techniques for wideband low-power Delta-Sigma analog-to-digital converters

Delta-Sigma (ΔΣ) analog-to-digital converters (ADCs) are traditionally used in high quality audio systems, instrumentation and measurement (I&M) and biomedical devices. With the continued downscaling of CMOS technology, they are becoming popular in wideband applications such as wireless and wired communication systems,high-definition television and radar systems. There are two general realizations of a ΔΣ modulator. One is based on the discrete-time (DT) switched-capacitor (SC) circuitry and the other employs continuous-time (CT) circuitry. Compared to a CT structure, the DT ΔΣ ADC is easier to analyze and design, is more robust to process variations and jitter noise, and is more flexible in the multi-mode applications. On the other hand, the CT ΔΣ ADC does not suffer from the strict settling accuracy requirement for the loop filter and thus can achieve lower power dissipation and higher sampling frequency than its DT counterpart. In this thesis, both DT and CT ΔΣ ADCs are investigated. Several design innovations, in both system-level and circuit-level, are proposed to achieve lower power consumption and wider signal bandwidth. For DT ΔΣ ADCs, a new dynamic-biasing scheme is proposed to reduce opamp bias current and the associated signal-dependent harmonic distortion is minimized by using the low-distortion architecture. The technique was verified in a 2.5MHz BW and 13bit dynamic range DT ΔΣ ADC. In addition, a second-order noise coupling technique is presented to save two integrators for the loop filter, and to achieve low power dissipation. Also, a direct-charge-transfer (DCT) technique is suggested to reduce the speed requirements of the adder, which is also preferable in wideband low-power applications. For CT ΔΣ ADCs, a wideband low power CT 2-2 MASH has been designed. High linearity performance was achieved by using a modified low-distortion technique, and the modulator achieves higher noise-shaping ability than the single stage structure due to the inter-stage gain. Also, the quantization noise leakage due to analog circuit non-idealities can be adaptively compensated by a designed digital calibration filter. Using a 90nm process, simulation of the modulator predicts a 12bit resolution within 20MHz BW and consumes only 25mW for analog circuitry. In addition, the noise-coupling technique is investigated and proposed for the design of CT ΔΣ ADCs and it is promising to achieve low power dissipation for wideband applications. Finally, the application of noise-coupling technique is extended and introduced to high-accuracy incremental data converters. Low power dissipation can be expected

High efficiency delta-sigma modulation data converters

Enabled by continued device scaling in CMOS technology, more and more functions that were previously realized in separate chips are getting integrated on a single chip nowadays. Integration on silicon has opened the door to new portable wireless applications, and initiated a widespread use of these devices in our common everyday life. Wide signal bandwidth, high linearity and dynamic range, and low power dissipation are required of embedded data converters that are the performance-limiting key building blocks of those systems. Thus, power-efficient and highly-linear data conversion over wide range of signal bands is essential to get the full benefits from device scaling. This continued trend keeps innovation in the design of data converter continuing. Traditionally, delta-sigma modulation data converters proved to be very effective in applications where high resolution was necessary in a relatively narrow signal band. There have been active research efforts across academia and industry on the extension of achievable signal bandwidth without compromising the performance of these data converters. In this dissertation, architectural innovations, combined with effective design techniques for delta-sigma modulation data converters, are presented to overcome the associated limitations. The effectiveness of the proposed approaches is demonstrated by test results for the following state-of-the-art prototype designs: (1) a 0.8 V, 2.6 mW, 88 dB dual-channel audio delta-sigma modulation D/A converter with headphone driver; (2) an 88 dB ring-coupled delta-sigma ADC with 1.9 MHz bandwidth and -102.4 dB THD; (3) a multi-cell noise-coupled delta-sigma ADC with 1.9 MHz bandwidth, 88 dB DR, and -98 dB THD; (4) an 8.1 mW, 82 dB self-coupled delta-sigma ADC with 1.9 MHz bandwidth and -97 dB THD; (5) a noise-coupled time-interleaved delta-sigma ADC with 4.2 MHz bandwidth, -98 dB THD, and 79 dB SNDR; (6) a noise-coupled time-interleaved delta-sigma ADC with 2.5 MHz bandwidth, -104 dB THD, and 81 dB SNDR. As an extension of this research, two novel architectures for efficient double-sampling delta-sigma ADCs and improved low-distortion delta-sigma ADC are proposed, and validated by extensive simulations.Keywords: improved low-distortion modulator, time interleaving, data converter, multi-cell ADC, efficient double sampling, noise coupling, delta-sigma modulatio