Implementation of Four Real-Time Software Defined Receivers and a Space-Time Decoder using Xilinx Virtex 2 Pro Field Programmable Gate Array

This paper describes the concept, architecture, development and demonstration of a real time, high performance, software defined 4-receiver system and a space time decoder to be implemented on a Xilinx Virtex 2 Pro Field Programmable Gate Array. It is designed and developed for research into receiver diversity and multiple input and multiple output (MIMO)wireless systems. Each receiver has a Freescale DSP56321 digital signal processor (DSP) to run synchronization, channel state estimation and equalization algorithms. The system is software defined to allow for flexibility in the choice of receiver demodulation formats, output data rates and space-time decoding schemes. Hardware, firmware and software aspects of the receiver and space time decoder system to meet design requirements are discussed

Implementation of Four Real-Time Software Defined Receivers and a Space-Time Decoder using Xilinx Virtex 2 Pro Field Programmable Gate Array

This paper describes the concept, architecture, development and demonstration of a real time, high performance, software defined 4-receiver system and a space time decoder to be implemented on a Xilinx Virtex 2 Pro Field Programmable Gate Array. It is designed and developed for research into receiver diversity and multiple input and multiple output (MIMO)wireless systems. Each receiver has a Freescale DSP56321 digital signal processor (DSP) to run synchronization, channel state estimation and equalization algorithms. The system is software defined to allow for flexibility in the choice of receiver demodulation formats, output data rates and space-time decoding schemes. Hardware, firmware and software aspects of the receiver and space time decoder system to meet design requirements are discussed

Optimization of DSSS Receivers Using Hardware-in-the-Loop Simulations

Over the years, there has been significant interest in defining a hardware abstraction layer to facilitate code reuse in software defined radio (SDR) applications. Designers are looking for a way to enable application software to specify a waveform, configure the platform, and control digital signal processing (DSP) functions in a hardware platform in a way that insulates it from the details of realization. This thesis presents a tool-based methodolgy for developing and optimizing a Direct Sequence Spread Spectrum (DSSS) transceiver deployed in custom hardware like Field Programmble Gate Arrays (FPGAs). The system model consists of a tranmitter which employs a quadrature phase shift keying (QPSK) modulation scheme, an additive white Gaussian noise (AWGN) channel, and a receiver whose main parts consist of an analog-to-digital converter (ADC), digital down converter (DDC), image rejection low-pass filter (LPF), carrier phase locked loop (PLL), tracking locked loop, down-sampler, spread spectrum correlators, and rectangular-to-polar converter. The design methodology is based on a new programming model for FPGAs developed in the industry by Xilinx Inc. The Xilinx System Generator for DSP software tool provides design portability and streamlines system development by enabling engineers to create and validate a system model in Xilinx FPGAs. By providing hierarchical modeling and automatic HDL code generation for programmable devices, designs can be easily verified through hardware-in-the-loop (HIL) simulations. HIL provides a significant increase in simulation speed which allows optimization of the receiver design with respect to the datapath size for different functional parts of the receiver. The parameterized datapath points used in the simulation are ADC resolution, DDC datapath size, LPF datapath size, correlator height, correlator datapath size, and rectangular-to-polar datapath size. These parameters are changed in the software enviornment and tested for bit error rate (BER) performance through real-time hardware simualtions. The final result presents a system design with minimum harware area occupancy relative to an acceptable BER degradation

Implementation of a Real-Time Beamforming System on Field Programmable Gate Array

Beamforming is an important technique in array signal processing and wireless communication systems. In this project, we investigate the Minimum Variance Distortionless Response (MVDR) beamforming technique and its implementation. The QR-RLS algorithm is chosen because of its advantages of numerical stability and systolic array architecture. The team successfully implemented the real-time beamforming of a linear array with 3 receiving antennas on a Xilinx Virtex-5 FPGA platform. Both the simulation and hardware implementation results are presented in this report

Implementaciones en Hardware de técnicas de Radiogoniometría

This paper presents a survey and a comparison between different radio direction finding implementations, leading to identify the best option for implementation of this feature in spectrum management activities for developing countries. The implementations analyzed include classic techniques like Pseudo-Doppler and advanced high-resolution techniques like MUSIC. Different hardware alternatives to implement the algorithms are presented, including SDR (Software Defined Radio), FPGA (Field Programmable Gate Array) and DSP (Digital Signal Processing). Also some hybrid configurations are included, where software and hardware are combined aiming to optimize time and cost resources. Finally some commercial applications are shown. These use angle of arrival, time difference of arrival and other parameters for triangulation or trilateration purposes.En este artículo se presenta una revisión bibliográfica y un análisis comparativo de implementaciones en hardware de técnicas de Radiogoniometría, también conocidas como Radio Direction Finding (RDF), que permiten identificar la mejor opción para implementar estas funcionalidad en actividades de gestión del espectro en países en vía de desarrollo. Dentro de las implementaciones tratadas se incluyen técnicas clásicas como Pseudo-Doppler y técnicas avanzadas de alta resolución como MUSIC. Se presentan diferentes alternativas de hardware para realizar las implementaciones las cuales incluyen SDR (Software Defined Radio), FPGA (Field Programmable Gate Array) y DSP (Digital Signal Processor); a la vez que se incluyen algunas configuraciones híbridas dónde se mezcla el software y el hardware con el fin de optimizar recursos de tiempo y dinero. Adicionalmente se muestran algunas aplicaciones comerciales que emplean técnicas de geolocalización basadas en información de ángulos de llegada, tiempos de llegada u otros parámetros que permiten realizar el proceso de triangulación o trilateración según sea el caso

Review of Recent Trends

This work was partially supported by the European Regional Development Fund (FEDER), through the Regional Operational Programme of Centre (CENTRO 2020) of the Portugal 2020 framework, through projects SOCA (CENTRO-01-0145-FEDER-000010) and ORCIP (CENTRO-01-0145-FEDER-022141). Fernando P. Guiomar acknowledges a fellowship from “la Caixa” Foundation (ID100010434), code LCF/BQ/PR20/11770015. Houda Harkat acknowledges the financial support of the Programmatic Financing of the CTS R&D Unit (UIDP/00066/2020).MIMO-OFDM is a key technology and a strong candidate for 5G telecommunication systems. In the literature, there is no convenient survey study that rounds up all the necessary points to be investigated concerning such systems. The current deeper review paper inspects and interprets the state of the art and addresses several research axes related to MIMO-OFDM systems. Two topics have received special attention: MIMO waveforms and MIMO-OFDM channel estimation. The existing MIMO hardware and software innovations, in addition to the MIMO-OFDM equalization techniques, are discussed concisely. In the literature, only a few authors have discussed the MIMO channel estimation and modeling problems for a variety of MIMO systems. However, to the best of our knowledge, there has been until now no review paper specifically discussing the recent works concerning channel estimation and the equalization process for MIMO-OFDM systems. Hence, the current work focuses on analyzing the recently used algorithms in the field, which could be a rich reference for researchers. Moreover, some research perspectives are identified.publishersversionpublishe

A low-complexity linear and iterative receiver architecture for multi-antenna communication systems

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004.Vita.Includes bibliographical references (leaves 60-62).Multi-antenna systems have been shown to significantly improve channel capacity in wireless environments. The focus of this thesis is on the design of low-complexity multi-antenna receiver architectures for communication networks and their demonstration in a real-time wireless environment. Our practical realization of an orthogonal frequency-division multi-antenna receiver is capable of several forms of linear and iterative detection. Our implementation is based on a division-free reformulation of standard minimum mean-squared-error detection algorithms and uses complex dot-products as the basic building blocks of a folded-pipelined architecture. This folded-pipelined architecture provides significant area savings over non-folded approaches. The demonstration of our receiver architecture is carried out on a rapid-prototyping FPGA communication system. This prototype is used to validate our design and complement theoretical and simulated results with real-time laboratory measurements in a typical office environment.by David Louis Milliner.M.Eng

Optimising and evaluating designs for reconfigurable hardware

Growing demand for computational performance, and the rising cost for chip design and manufacturing make reconfigurable hardware increasingly attractive for digital system implementation. Reconfigurable hardware, such as field-programmable gate arrays (FPGAs), can deliver performance through parallelism while also providing flexibility to enable application builders to reconfigure them. However, reconfigurable systems, particularly those involving run-time reconfiguration, are often developed in an ad-hoc manner. Such an approach usually results in low designer productivity and can lead to inefficient designs. This thesis covers three main achievements that address this situation. The first achievement is a model that captures design parameters of reconfigurable hardware and performance parameters of a given application domain. This model supports optimisations for several design metrics such as performance, area, and power consumption. The second achievement is a technique that enhances the relocatability of bitstreams for reconfigurable devices, taking into account heterogeneous resources. This method increases the flexibility of modules represented by these bitstreams while reducing configuration storage size and design compilation time. The third achievement is a technique to characterise the power consumption of FPGAs in different activity modes. This technique includes the evaluation of standby power and dedicated low-power modes, which are crucial in meeting the requirements for battery-based mobile devices