CMOS design of chaotic oscillators using state variables: a monolithic Chua's circuit

This paper presents design considerations for monolithic implementation of piecewise-linear (PWL) dynamic systems in CMOS technology. Starting from a review of available CMOS circuit primitives and their respective merits and drawbacks, the paper proposes a synthesis approach for PWL dynamic systems, based on state-variable methods, and identifies the associated analog operators. The GmC approach, combining quasi-linear VCCS's, PWL VCCS's, and capacitors is then explored regarding the implementation of these operators. CMOS basic building blocks for the realization of the quasi-linear VCCS's and PWL VCCS's are presented and applied to design a Chua's circuit IC. The influence of GmC parasitics on the performance of dynamic PWL systems is illustrated through this example. Measured chaotic attractors from a Chua's circuit prototype are given. The prototype has been fabricated in a 2.4- mu m double-poly n-well CMOS technology, and occupies 0.35 mm/sup 2/, with a power consumption of 1.6 mW for a +or-2.5-V symmetric supply. Measurements show bifurcation toward a double-scroll Chua's attractor by changing a bias current

Design and implementation of 30kW 200/900V LCL modular multilevel based DC/DC converter for high power applications

This paper presents the design, development and testing of a 30kW, 200V/900V modular multilevel converter (MMC) based DC/DC converter prototype. An internal LCL circuit is used to provide voltage stepping and fault tolerance property. The converter comprises two five level MMC based on insulated gate bipolar transistors (IGBTs) and metal oxide semiconductor field effect transistor (MOSFET). Due to low number of levels, selective harmonic elimination modulation (SHE) is used, which determines the switching angles in such a way that third harmonic is minimized whereas the fundamental component is a linear function of the modulation index. In addition, instead of using an expensive control board, three commercial control boards are embedded. This is required to implement the sophisticated DC/DC converter control algorithm. Simulation and experimental results are presented to demonstrate the converter performance in step up and down modes

Assessment of ecosystem integrity of lowland dipterocarp forest ecosystem using remote sensing

Ecosystem Integrity Index (EII) is a concept to determine the quality or the health of an ecosystem. The EII development can assist forest managers and decision makers in the conservation effort and forest management in Malaysia through the development of a simple and easy-to-adopt index. The aim of this study is to assess and evaluate the EII through the development of forest structure empirical models from remotely sensed data for lowland dipterocarp forest in Malaysia. The objectives of this study are: (i) to assess the structure and composition of lowland dipterocarp forest in Malaysia, (ii) to develop empirical model for estimating stand structure from remotely sensed data, and (iii) to derive the ecosystem integrity index for lowland dipterocarp forest. Tree Basal Area (BA), aboveground biomass (AGB) and volume plot from plot data were used as dependent variables, while remote sensing data from Landsat, Pleiades and LiDAR were used as independent variables for model development. Tree plot census was carried out from 17 to 19 May 2016, while remote sensing data acquisition dates for Landsat, Pleiades and LiDAR were 13 March 2016, 24 January 2015 and April 2015 respectively. Forest Structure Modeling was carried out by means of a correlation analysis with the calibration of dependent and independent data to select the most significant and accurate remote sensing variables to derive empiric equation (model), fitting stage to select the best model with the highest coefficient of determination (R2) and the lowest root mean square error ( RMSE) validation of the final selected. The Ecosystem Integrity Index was developed by the average percentage of the predicted BA, AGB and model volume. The EII was categorised at five integrity levels as high (81–100%), medium high (61–80%), moderate (41–60%), medium low (21–40%) and low (0–20%). A total of 1035 trees with diameter at breast height (DBH) of 5.0 cm and above were recorded in 69.115 ha sampling areas. The total trees recorded represented 150 species from 87 genera and 34 families. Shorea macroptera (Dipterocarpaceae), S. leprosula (Dipterocarpaceae) and S. parviflora (Dipterocarpaceae) are three dominant species, with Species Important Value Index (SIVi) of 6.49%, 6.23% and 5.51%, respectively. Dipterocarpaceae is the most dominant with Family Important Value Index (FIVi) of 33.54%. The developed final model is robust and consistent with high R2 with range of 0.84 to 0.87. The final models constructed for AGB, BA and volume value of R2 are 0.85, 0.84 and 0.87 respectively. The RMSE of AGB, BA and volume model are 53.1 Mg/ha, 3.54 m2/ha and 46.4 m3/ha, respectively. The overall stand AGB, BA and volume for Sungai Menyala Forest Reserve is 282.29 Mg/ha, 17.68 m2/ha and 239.51 m3/ha. An Ecosystem Integrity Index (EII) assessment has been successfully demonstrated by this study with production of practical, multi-scaled, flexible, adjustable and policy-relevant index. The overall EII of Sungai Menyala Forest Reserve is in Category 3, which shows that the area is within the medium value

Single-amplifier integrator-based low power CMOS filter for video frequency applications

“This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder." “Copyright IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.”This paper describes a new low power fully differential second-order continuous-time low pass filter for use at video frequencies. The filter uses a single active device in combination with MOSFET resistors and grounded capacitors to achieve very low power consumption, small chip area and large dynamic range. The ideal integrator is realised using an internally compensated opamp consisting of only current mirrors and voltage buffers, whilst the lossy integrator is implemented by a single passive RC circuit. The filter has been simulated using a CMOS process. Results show that with a single 5 V power supply, cut-off frequency can be tuned from 3.5 MHz to 8 MHz, dynamic range is better than 67 dB, and power consumption is less than 1.7 mW

Switching-Cell Arrays - An Alternative Design Approach in Power Conversion

© 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting /republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other worksThe conventional design of voltage-source power converters is based on a two-level half-bridge configuration and the selection of power devices designed to meet the full application specifications (voltage, current, etc.). This leads to the need to design and optimize a large number of different devices and their ancillary circuitry and prevents taking advantage from scale economies. This paper proposes a paradigm shift in the design of power converters through the use of a novel configurable device consisting on a matrix arrangement of highly-optimized switching cells at a single voltage class. Each switching cell consists of a controlled switch with antiparallel diode together with a self-powered gate driver. By properly interconnecting the switching cells, the switching cell array (SCA) can be configured as a multilevel active-clamped leg with different number of levels. Thus, the SCA presents adjustable voltage and current ratings, according to the selected configuration. For maximum compactness, the SCA can be conceived to be only configurable by the device manufacturer upon the customer needs. For minimum cost, it can also be conceived to be configurable by the customer, leading to field-configurable SCAs. Experimental results of a 6x3 field-configurable SCA are provided to illustrate and validate this design approach.Peer ReviewedPostprint (author's final draft

Systematic Comparison of HF CMOS Transconductors

Transconductors are commonly used as active elements in high-frequency (HF) filters, amplifiers, mixers, and oscillators. This paper reviews transconductor design by focusing on the V-I kernel that determines the key transconductor properties. Based on bandwidth considerations, simple V-I kernels with few or no internal nodes are preferred. In a systematic way, virtually all simple kernels published in literature are generated. This is done in two steps: 1) basic 3-terminal transconductors are covered and 2) then five different techniques to combine two of them in a composite V-I kernel. In order to compare transconductors in a fair way, a normalized signal-to-noise ratio (NSNR) is defined. The basic V-I kernels and the five classes of composite V-I kernels are then compared, leading to insight in the key mechanisms that affect NSNR. Symbolic equations are derived to estimate NSNR, while simulations with more advanced MOSFET models verify the results. The results show a strong tradeoff between NSNR and transconductance tuning range. Resistively generated MOSFETs render the best NSNR results and are robust for future technology developments

High Input Impedance Voltage-Mode Universal Biquadratic Filters With Three Inputs Using Three CCs and Grounding Capacitors

Two current conveyors (CCs) based high input impedance voltage-mode universal biquadratic filters each with three input terminals and one output terminal are presented. The first circuit is composed of three differential voltage current conveyors (DVCCs), two grounded capacitors and four resistors. The second circuit is composed of two DVCCs, one differential difference current conveyor (DDCC), two grounded capacitors and four grounded resistors. The proposed circuits can realize all the standard filter functions, namely, lowpass, bandpass, highpass, notch and allpass filters by the selections of different input voltage terminals. The proposed circuits offer the features of high input impedance, using only grounded capacitors and low active and passive sensitivities. Moreover, the x ports of the DVCCs (or DDCC) in the proposed circuits are connected directly to resistors. This design offers the feature of a direct incorporation of the parasitic resistance at the x terminal of the DVCC (DDCC), Rx, as a part of the main resistance

Near-Zero-Power Temperature Sensing via Tunneling Currents Through Complementary Metal-Oxide-Semiconductor Transistors.

Temperature sensors are routinely found in devices used to monitor the environment, the human body, industrial equipment, and beyond. In many such applications, the energy available from batteries or the power available from energy harvesters is extremely limited due to limited available volume, and thus the power consumption of sensing should be minimized in order to maximize operational lifetime. Here we present a new method to transduce and digitize temperature at very low power levels. Specifically, two pA current references are generated via small tunneling-current metal-oxide-semiconductor field effect transistors (MOSFETs) that are independent and proportional to temperature, respectively, which are then used to charge digitally-controllable banks of metal-insulator-metal (MIM) capacitors that, via a discrete-time feedback loop that equalizes charging time, digitize temperature directly. The proposed temperature sensor was integrated into a silicon microchip and occupied 0.15 mm2 of area. Four tested microchips were measured to consume only 113 pW with a resolution of 0.21 °C and an inaccuracy of ±1.65 °C, which represents a 628× reduction in power compared to prior-art without a significant reduction in performance