Development of advanced technologies for the fabrication of III-V high electron mobility transistors

Over the past 5 years there has been an increase in the number of applications that require devices that operate in the millimetre range (30-300GHz). This demand has driven research into " devices that will operate at frequencies above 100GHz. This performance has been achieved using two main technologies, the Heterojunction Bipolar Transistor (HBT) and the High Electron Mobility Transistor (HEMT). At present it is a HEMT device that holds the record for the highest operating frequency of any transistor. It is this technology that this project concentrates on. In order to fabricate devices that operate at these frequencies two methods are commonly employed. The first is to vary the material of the device, in particular, increasing the indium content of the channel. The second method is to reduce the physical dimensions of the transistors, including reducing the gate length of the device therefore reducing transit time and gate capacitance. Reducing the separation of the source-drain ohmic contacts or employing a self-aligned ohmic strategy reduces the associated parasitic resistances. This project will concentrate on the scaling of the gate length in addition to the reduction of parasitic resistances with the use of self-aligned ohmic contacts.This work includes the realisation of the first self-aligned 120nm T -Gate. GaAs pHEMT fabricated at the University of Glasgow. These devices required the development of two key technologies, the non-annealed ohmic contact and the succinic acid based selective wet etch. The self-aligned devices showed good RF performance with a ft of 150 GHz and a fmax of 180 GHz which compares favourable with results o~ 120nm GaAs pHEMTs previously fabricated at Glasgow. The investigation of gate length scaling to device performance included the development of two lithographic process capable of producing HEMT with a gate length of 50nm and 30nm respectively in addition to a method ~f sample preparation that allows these devices to be analysed using TEM techniques. This work has lead to the realisation of SOnm T -gate metamorphic HEMTs using a PMMAIcopolymer resist stack, these devices displayed an excellent yield, with over 95% of devices working. The uniformity of the gate process was also high with a threshold voltage of - 0.44SV with a standard deviation of O.OOSV. The devices demonstrated an .it of 330GHz and a fmax of 260GHz making these devices some of the fastest transistors that have ever been fabricated on a GaAs substrate. The second lithography process was developed to realise T -gates with a gate length of less than SOnm. This processed used a two stage "bi-lithography" process to minimise the effect of forward s7attering through the resist. The gate footprint was transferred into a Si02 gate by a dry etch process. This lithography process was integrated into a full process flow for lattice matched InP HEMTs Using this process, HEMTs were fabricated with a T-gate of 2Snm. This is the smallest T -gate device that has been fabricated at the University of Glasgow and is comparable with the smallest HEMT devices in the world

Millimeter-wave GaN high electron mobility transistors and their integration with silicon electronics

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2011.Cataloged from PDF version of thesis.Includes bibliographical references.In spite of the great progress in performance achieved during the last few years, GaN high electron mobility transistors (HEMTs) still have several important issues to be solved for millimeter-wave (30 ~ 300 GHz) applications. One of the key challenges is to improve its high frequency characteristics. In this thesis, we particularly focus on fT and fma, two of the most important figures of merit in frequency performance of GaN HEMTs and investigate them both analytically and experimentally. Based on an improved physical understanding and new process technologies, we aim to demonstrate the state-of-the-art high frequency performance of GaN HEMTs. To maximize fmax, parasitic components in the device (Ri, R, Rg, Cgd, and go) are carefully minimized and the optimized 60-nm AlGaN/GaN HEMT shows a very high fmax of 300 GHz. The lower-than-expected fT observed in many AlGaN/GaN HEMTs is attributed to a significant drop of the intrinsic transconductance at high frequency (RF gm) with respect to the intrinsic DC g. (called RF gm-collapse). By suppressing RF gm-collapse and harmoniously scaling the device, a record fT of 225 GHz is achieved in the 55-nm AlGaN/GaN HEMT. Another important challenge for the wide adoption of GaN devices is to develop suitable technology to integrate these GaN transistors with Si(100) electronics. In this thesis, we demonstrate a new technology to integrate, for the first time, GaN HEMTs and Si(100) MOSFETs on the same chip. This integration enables the development of hybrid circuits that take advantage of the high-frequency and power capability of GaN and the unsurpassed circuit scalability and complexity of Si electronics.by Jinwook W. Chung.Ph.D

Selective lateral nano-epitaxy for manufacturable nanowire electronics

This dissertation provides a comprehensive study on vapor-liquid-solid (VLS) growth of III-V planar nanowires and their electronic device applications. III-V materials, especially high-In-content InGaAs, are considered as a very promising n-channel material candidate for post-Si complementary metal-oxide-semiconductor (CMOS) technology due to their excellent electron mobility. Semiconductor nanowires are of interest for electronic device applications primarily due to their 3D nature which facilitates realization of multi-gate field effect transistors (FETs). VLS growth, where a metallic seed nanoparticle is used to gather materials and guide nanowire growth, is a unique bottom-up method suitable for synthesizing extremely thin nanowires with high aspect ratios and axially uniform diameters. Unlike conventional VLS nanowires which grow along out-of-plane directions with respect to the substrate surface, the recently emerged planar VLS growth produces III-V nanowires self-aligned along certain in-plane crystal directions and epitaxially attached to substrates. This particular type of VLS growth is called Selective Lateral nano-Epitaxy (SLE), where the selectivity is provided by seed nanoparticles. Those planar nanowires are compatible with the well-established planar processing technology and are therefore a potential solution to realizing manufacturable nanowire-based integrated circuits. In this dissertation, homogeneous GaAs planar nanowire arrays with perfect yield of planar growth, which are ready for practical device and circuit applications, are developed. The array-based GaAs planar nanowire growth also enables systematic growth studies, based on which the underlying mechanism responsible for the planar type of growth is proposed. In addition to homogeneous growth, heterogeneous SLE of high-quality planar InAs nanowires on GaAs is demonstrated. On the application side, GaAs planar nanowire tri-gate MOSFETs and a current-source loaded amplifier circuit based on nanowire MESFETs are presented. Gate-all-around (GAA) InAs planar nanowire MOSFETs are developed and analyzed. Chapter 1 discusses the motivation behind researching III-V materials and semiconductor nanowires for future low-power and high-performance nano-electronics. Chapter 2 introduces the planar type of VLS growth—Selective Lateral nano-Epitaxy—and compares it with the top-down nanowire fabrication technology. Chapter 3 presents the array-based GaAs planar nanowire growth and detailed growth mechanism studies intended to reveal the underlying reasons leading to the planar version of VLS growth. Chapter 4 demonstrates GaAs planar nanowire tri-gate n-MOSFETs with Al2O3 as gate dielectric material and a high voltage-gain amplifier circuit based on GaAs planar nanowire MESFETs. Chapter 5 presents the growth and material characterizations of heterogeneous InAs planar nanowires on GaAs substrate. InAs nanowire GAA MOSFETs are then presented with detailed device analysis. Chapter 6 outlines several future research directions including InAs nanowire MOSFET performance improvement, heterogeneous InAs planar nanowire growth yield improvement, and heterogeneous integration of different types of nanowires

DYNAMIC RANGE LIMITATIONS OF LOW-NOISE MICROWAVE TRANSISTORS AT CRYOGENIC TEMPERATURES

Dynamic range is an important metric that specifies the limits of input signal amplitude for the ideal operation of a given receiver. The low end of dynamic range is defined by the noise floor whereas the upper limit is determined by large-signal distortion. While dynamic range can be predicted in the temperature range where compact transistor models are valid, the lack of large-signal models at temperatures below -55 C prevents the prediction and optimization of dynamic range for applications that require cryogenic cooling. For decades, the main goal concerning the performance of these applications was lowering the noise floor of cryogenic receiver front-ends. For this, linear small-signal noise models have been extensively studied and used for designs of low-noise amplifiers. In this work, the existing small-signal noise modeling approach is extended to capture the weakly nonlinear properties of the transistors that are commonly used in cryogenic amplification. Indium phosphide high electron mobility transistors and silicon germanium heterojunction bipolar transistors are considered. The goal of this work is to identify the fundamental dynamic range limitations of these transistors such that the results are not device specific, but applicable to the corresponding device families. Identifying the fundamental limitations of dynamic range in a semiconductor device requires a broad understanding of physical properties of the transistors. For this, a theoretical analysis will be presented first as a function of temperature. The small-signal noise modeling will then be discussed using techniques that are well recognized in the literature. This will be followed by an explanation of the nonlinear modeling approach used in this work. This approach relies on the definition of Taylor series expansion coefficients of the dominant nonlinear mechanisms of the transistors. The modeling results will be interpreted with respect to the initially presented theoretical framework. Finally, the dynamic range performance will be studied as a function of source and load terminations. In addition to this systematic approach to understanding the physical limitations of dynamic range, model to measurement agreement of broadband cryogenic amplifiers will also be presented which will verify the accuracy of the modeling approach

Study of High-k Dielectrics and their Interfaces on Semiconductors for Device Applications

This thesis has focused on two emerging applications of high-k dielectrics in Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) and in Metal-InsulatorSemiconductor High Electron Mobility Transistors (MIS-HEMTs). The key aim has been to propose the best routes for passivation of semiconductor/high-k oxide interfaces by investigating the band alignments and interface properties of several oxides, such as Tm2O3, Ta2O5, ZrO2, Al2O3 and MgO, deposited on different semiconductors: Si, Ge, GaN, InGaAs and InGaSb. The electrical characterisation of fabricated MIS capacitor and (MIS)-HEMT devices have also been performed. Thulium silicate (TmSiO) has been identified as a promising candidate for integration as interfacial layer (IL) in HfO2/TiN MOSFETs. The physical properties of Tm2O3/IL/Si interface have been elucidated, where IL (TmSiO) has been formed using different post-deposition annealing (PDA) temperatures, from 550 to 750 °C. It has been found that the best-scaled stack (sub-nm IL) is formed at 550 °C PDA with a graded interface layer and a strong SiOx (Si 3+) component. A large valence band offset (VBO) of 2.8 eV and a large conduction band offset (CBO) of 1.9 eV have been derived for Tm2O3/Si by X-ray photoelectron spectroscopy (XPS) and variable angle spectroscopic ellipsometry. Further increase of device performance can be achieved by replacing Si with GaN for high frequency, high power and high-temperature operation. In this thesis, several GaN cleaning procedures have been considered: 30% NH4OH, 20% (NH4)2S, and 37% HCl. It has been found that the HCl treatment shows the lowest oxygen contamination and Garich surface, and hence has been used prior sputtering of Ta2O5, Al2O3, ZrO2 and MgO on GaN. The large VBOs of 1.1 eV and 1.2 eV have been derived for Al2O3 and MgO on GaN respectively, using XPS and Kraut’s method; the corresponding CBOs are 2.0 eV and 2.8 eV respectively, taking into account the band gaps of Al2O3 (6.5 eV) and MgO (7.4 eV) determined from XPS O 1s electron energy spectra. The lowest leakage currents were obtained for devices with Al2O3 and MgO, i.e. 5.3 ×10-6 A/cm2 and 3.2 ×10-6 A/cm2 at 1 V, respectively in agreement with high band offsets (> 1 eV). Furthermore, the effect of different surface treatments (HCl, O2 plasma and 1-Octadecanethiol (ODT)) prior to atomic layer deposition of Al2O3 on the GaN/AlGaN/GaN heterostructure has been investigated. The MIS-HEMTs fabricated using the low-cost ODT GaN surface treatment have been found to exhibit superior performance for power switching applications such as a low threshold voltage, VT of -12.3 V, hysteresis of 0.12 V, a small subthreshold voltage slope (SS) of 73 mV/dec, and a low density of interface states, Dit of 3.0 x10^12 cm-2eV-1. A comprehensive novel study of HfO2/InGaAs and Al2O3/InGaSb interfaces have also been conducted for use in III-V based MOSFETs. The addition of the plasma H2/TMA/H2 pre-cleaning has been found to be very effective in recovering etch damage on InGaAs, especially for (110) orientation, and led to the improvement of electrical characteristics. Furthermore, the combination of H2 plasma exposure and forming gas anneal yielded significantly improved metrics for Al2O3/InGaSb over the control HCltreated sample, with the 150 W plasma treatment giving both the highest capacitance and the lowest stretch out

Vertical Heterostructure III-V MOSFETs for CMOS, RF and Memory Applications

This thesis focuses mainly on the co-integration of vertical nanowiren-type InAs and p-type GaSb MOSFETs on Si (Paper I & II), whereMOVPE grown vertical InAs-GaSb heterostructure nanowires areused for realizing monolithically integrated and co-processed all-III-V CMOS.Utilizing a bottom-up approach based on MOVPE grown nanowires enablesdesign flexibilities, such as in-situ doping and heterostructure formation,which serves to reduce the amount of mask steps during fabrication. By refiningthe fabrication techniques, using a self-aligned gate-last process, scaled10-20 nm diameters are achieved for balanced drive currents at Ion ∼ 100μA/μm, considering Ioff at 100 nA/μm (VDD = 0.5 V). This is enabledby greatly improved p-type MOSFET performance reaching a maximumtransconductance of 260 μA/μm at VDS = 0.5 V. Lowered power dissipationfor CMOS circuits requires good threshold voltage VT matching of the n- andp-type device, which is also demonstrated for basic inverter circuits. Thevarious effects contributing to VT-shifts are also studied in detail focusing onthe InAs channel devices (with highest transconductance of 2.6 mA/μm), byusing Electron Holography and a novel gate position variation method (PaperV).The advancements in all-III-V CMOS integration spawned individual studiesinto the strengths of the n- and p-type III-V devices, respectively. Traditionallymaterials such as InAs and InGaAs provide excellent electrontransport properties, therefore they are frequently used in devices for highfrequency RF applications. In contrast, the III-V p-type alternatives have beenlacking performance mostly due to the difficult oxidation properties of Sb-based materials. Therefore, a study of the GaSb properties, in a MOSFETchannel, was designed and enabled by new manufacturing techniques, whichallowed gate-length scaling from 40 to 140 nm for p-type Sb-based MOSFETs(Paper III). The new fabrication method allowed for integration of deviceswith symmetrical contacts as compared to previous work which relied on atunnel-contact at the source-side. By modelling based on measured data fieldeffecthole mobility of 70 cm2/Vs was calculated, well in line with previouslyreported studies on GaSb nanowires. The oxidation properties of the GaSbgate-stack was further characterized by XPS, where high intensities of xraysare achieved using a synchrotron source allowed for characterization ofnanowires (Paper VI). Here, in-situ H2-plasma treatment, in parallel with XPSmeasurements, enabled a study of the time-dependence during full removalof GaSb native oxides.The last focus of the thesis was building on the existing strengths of verticalheterostructure III-V n-type (InAs-InGaAs graded channel) devices. Typically,these devices demonstrate high-current densities (gm >3 mS/μm) and excellentmodulation properties (off-state current down to 1 nA/μm). However,minimizing the parasitic capacitances, due to various overlaps originatingfrom a low access-resistance design, has proven difficult. Therefore, newmethods for spacers in both the vertical and planar directions was developedand studied in detail. The new fabrication methods including sidewall spacersachieved gate-drain capacitance CGD levels close to 0.2 fF/μm, which isthe established limit by optimized high-speed devices. The vertical spacertechnology, using SiO2 on the nanowire sidewalls, is further improved inthis thesis which enables new co-integration schemes for memory arrays.Namely, the refined sidewall spacer method is used to realize selective recessetching of the channel and reduced capacitance for large array memoryselector devices (InAs channel) vertically integrated with Resistive RandomAccess Memory (RRAM) memristors. (Paper IV) The fabricated 1-transistor-1-memristor (1T1R) demonstrator cell shows excellent endurance and retentionfor the RRAM by maintaining constant ratio of the high and low resistive state(HRS/LRS) after 106 switching cycles

Electrical Characterisation of III-V Nanowire MOSFETs

The ever increasing demand for faster and more energy-efficient electricalcomputation and communication presents severe challenges for the semiconductor industry and particularly for the metal-oxidesemiconductorfield-effect transistor (MOSFET), which is the workhorse of modern electronics. III-V materials exhibit higher carrier mobilities than the most commonly used MOSFET material Si so that the realisation of III-V MOSFETs can enable higher operation speeds and lower drive voltages than that which is possible in Si electronics. A lowering of the transistor drive voltage can be further facilitated by employing gate-all-around nanowire geometries or novel operation principles. However, III-V materials bring about their own challenges related to material quality and to the quality of the gate oxide on top of a III-V MOSFET channel.This thesis presents detailed electrical characterisations of two types of (vertical) III-V nanowire transistors: MOSFETs based on conventional thermionic emission; and Tunnel FETs, which utilise quantum-mechanical tunnelling instead to control the device current and reach inverse subthreshold slopes below the thermal limit of 60 mV/decade. Transistor characterisations span over fourteen orders of magnitude in frequency/time constants and temperatures from 11 K to 370 K.The first part of the thesis focusses on the characterisation of electrically active material defects (‘traps’) related to the gate stack. Low-frequency noise measurements yielded border trap densities of 10^18 to 10^20 cm^-3 eV^-1 and hysteresis measurements yielded effective trap densities – projected to theoxide/semiconductor interface – of 2x10^12 to 3x10^13 cm^-2 eV^-1. Random telegraph noise measurements revealed that individual oxide traps can locally shift the channel energy bands by a few millielectronvolts and that such defects can be located at energies from inside the semiconductor band gap all the way into the conduction band.Small-signal radio frequency (RF) measurements revealed that parts of the wide oxide trap distribution can still interact with carriers in the MOSFET channel at gigahertz frequencies. This causes frequency hystereses in the small-signal transconductance and capacitances and can decrease the RF gains by a few decibels. A comprehensive small-signal model was developed, which takes into account these dispersions, and the model was applied to guide improvements of the physical structure of vertical RF MOSFETs. This resulted in values for the cutoff frequency fT and the maximum oscillation frequency fmax of about 150 GHz in vertical III-V nanowire MOSFETs.Bias temperature instability measurements and the integration of (lateral) III-V nanowire MOSFETs in a back end of line process were carried out as complements to the main focus of this thesis. The results of this thesis provide a broad perspective of the properties of gate oxide traps and of the RF performance of III-V nanowire transistors and can act as guidelines for further improvement and finally the integration of III-V nanowire MOSFETs in circuits

Three-dimensional field-effect transistors with top-down and bottom-up nanowire-array channels

This dissertation research effort explores new transistor topologies using three-dimensional nanowire (NW)-array channels formed by both bottom-up and top-down synthesis. The bottom-up NW research centers on the Au-catalyzed planar GaAs NW assembly discovered at the University of Illinois Urbana-Champaign (UIUC). The top-down NW research approach involves plasma etching of an emerging wide-bandgap material, Gallium Oxide (Ga2O3), to make arrays of NW channels (or fins) for high-power electronics. Bottom-up AlGaAs/GaAs heterostructure core-shell planar NWs are demonstrated on a wafer scale with excellent yield. Their placement is determined by lithographically patterning an array of Au seeds on semi-insulating GaAs substrate. The GaAs NWs assemble by lateral epitaxy via a vapor-liquid-solid mechanism and align in parallel arrays as a result of the (100) GaAs crystal plane orientation; then, a thin-film AlGaAs layer conforms to the GaAs NWs to form AlGaAs/GaAs NW high-electron mobility channels. Radio frequency (RF) transistors are fabricated and show excellent dc and high-frequency performance. An fmax > 75 GHz with 104 is measured which is superior compared to carbon-based nanoelectronics and “spin-on III-V NWs”. A comprehensive small-signal model is used to extract the contributing and limiting factors to the RF performance of AlGaAs/GaAs NW-array transistors and predict future performance. Finally, a process is developed to show that III-V NWs on sacrificial epitaxial templates can be transferred to arbitrary substrates. Top-down NWs were formed from Sn-doped Ga2O3 homoepitaxially grown on semi-insulating beta-phase Ga2O3 substrates by metal-organic vapor phase epitaxy. First, conventional planar transistors were fabricated from a sample set to characterize and understand the electrical performance as a function of Sn-doping and epitaxial channel thickness. Second, the high-critical field strength was evaluated to highlight the benefit of using Ga2O3 as a disruptive technology to GaN and SiC. Lastly, the planar transistor results feed into a design for a top-down NW-array transistor. The Ga2O3 NW-arrays were formed by BCl3 plasma etching. A new wrap-gate transistor demonstrates normally-off (enhancement-mode) operation with a high breakdown voltage exceeding 600 V which is superior to any transistor using a 3D channel