Challenges and Approaches in Green Data Center

Cloud computing is a fast evolving area of information and communication technologies (ICTs)that hascreated new environmental issues. Cloud computing technologies have a widerange ofapplications due to theirscalability, dependability, and trustworthiness, as well as their abilityto deliver high performance at a low cost.The cloud computing revolution is altering modern networking, offering both economic and technologicalbenefits as well as potential environmental benefits. These innovations have the potential to improve energyefficiency while simultaneously reducing carbon emissions and e-waste. These traits have thepotential tomakecloud computing more environmentally friendly. Green cloud computing is the science and practise of properlydesigning, manufacturing, using, and disposing of computers, servers,and associated subsystems like displays,printers, storage devices, and networking and communication systems while minimising or eliminatingenvironmental impact. The most significant reason for a data centre review is to understand capacity,dependability, durability,algorithmic efficiency, resource allocation, virtualization, power management, andother elements. The green cloud design aims to reduce data centre power consumption. The main advantageof green cloud computing architecture is that it ensures real-time performance whilereducing IDC’s energyconsumption (internet data center).This paper analyzed the difficultiesfaced by data centers such as capacityplanning and management, up-time and performance maintenance, energy efficiency and cost cutting, realtime monitoring and reporting. The solution for the identified problems with DCIM system is also presentedin this paper. Finally, it discusses the market report’s coverage of green data centres, green computingprinciples, andfuture research challenges. This comprehensive green cloud analysis study will assist nativegreen research fellows in learning about green cloud concerns and understanding future research challengesin the field

Ultra-Low-Power Embedded SRAM Design for Battery- Operated and Energy-Harvested IoT Applications

Internet of Things (IoT) devices such as wearable health monitors, augmented reality goggles, home automation, smart appliances, etc. are a trending topic of research. Various IoT products are thriving in the current electronics market. The IoT application needs such as portability, form factor, weight, etc. dictate the features of such devices. Small, portable, and lightweight IoT devices limit the usage of the primary energy source to a smaller rechargeable or non-rechargeable battery. As battery life and replacement time are critical issues in battery-operated or partially energy-harvested IoT devices, ultra-low-power (ULP) system on chips (SoC) are becoming a widespread solution of chip makers’ choice. Such ULP SoC requires both logic and the embedded static random access memory (SRAM) in the processor to operate at very low supply voltages. With technology scaling for bulk and FinFET devices, logic has demonstrated to operate at low minimum operating voltages (VMIN). However, due to process and temperature variation, SRAMs have higher VMIN in scaled processes that become a huge problem in designing ULP SoC cores. This chapter discusses the latest published circuits and architecture techniques to minimize the SRAM VMIN for scaled bulk and FinFET technologies and improve battery life for ULP IoT applications

A new wireless asynchronous data communications module for industrial applications

All the sensors such as temperature, humidity, and pressure used in industry provide analog outputs as inputs for their control units. Wireless transmission of the data has advantages on wired transmission such as USB port, parallel port and serial port and therefore has great importance for industrial applications. In this work, a new wireless asynchronous data communications module has been developed to send the earth magnetic field data around a ferromagnetic material detected by a KMZ51 AMR sensor. The transmitter module transmits the analog data obtained from a source to a computer environment where they are stored and then presented in a graphical form. In this design, an amplitude shift keying (ASK) transceiver working at the frequency of 433.92 MHz which is a frequency inside the so called Industrial Scientific Medical band (ISM band) used for wireless communications. The analog data first fed into a 10-bit ADC controlled by a PIC microcontroller and then the digital data is sent to the transmitter. A preamble bit string is added in front of the data bits and another bit string for achieving synchronization and determination the start of the data is used. The data arriving at the receiver is taken by the microcontroller and sent to a LCD display as well as the serial port of a computer where it is written in a text file. A Visual Basic based graphics interface is designed to receive, store and present the data in the form of graphical shapes. In the paper, all the work has been explained in detail. © 2013 Published by Elsevier Ltd. All rights reserved

Circuits and Systems Advances in Near Threshold Computing

Modern society is witnessing a sea change in ubiquitous computing, in which people have embraced computing systems as an indispensable part of day-to-day existence. Computation, storage, and communication abilities of smartphones, for example, have undergone monumental changes over the past decade. However, global emphasis on creating and sustaining green environments is leading to a rapid and ongoing proliferation of edge computing systems and applications. As a broad spectrum of healthcare, home, and transport applications shift to the edge of the network, near-threshold computing (NTC) is emerging as one of the promising low-power computing platforms. An NTC device sets its supply voltage close to its threshold voltage, dramatically reducing the energy consumption. Despite showing substantial promise in terms of energy efficiency, NTC is yet to see widescale commercial adoption. This is because circuits and systems operating with NTC suffer from several problems, including increased sensitivity to process variation, reliability problems, performance degradation, and security vulnerabilities, to name a few. To realize its potential, we need designs, techniques, and solutions to overcome these challenges associated with NTC circuits and systems. The readers of this book will be able to familiarize themselves with recent advances in electronics systems, focusing on near-threshold computing

A study on coarse-grained placement and routing for low-power FPGA architecture

制度:新 ; 報告番号:甲3603号 ; 学位の種類:博士(工学) ; 授与年月日:2012/3/15 ; 早大学位記番号:新595

LOW POWER CONSUMED MULTIPLIER DESIGN BY ANT ARCHITECTURE WITH FIXED WIDTH REPLICA REDUNDANCY BLOCK

In this paper, we propose a dependable low-control multiplier configuration by receiving algorithmic commotion tolerant (ANT) engineering with the settled width multiplier to assemble the lessened accuracy copy excess square (RPR). The proposed ANT engineering can take care of the demand of high accuracy, low power utilization, and zone proficiency. We plan the settled width RPR with mistake remuneration circuit by means of examining of likelihood and insights. Utilizing the halfway item terms of information remedy vector and minor info redress vector to bring down the truncation blunders, the equipment unpredictability of mistake pay circuit can be improved. In a 12 × 12 bit ANT multiplier, circuit zone in our settled width RPR can be brought down by 44.55% and control utilization in our ANT configuration can be spared by 23% as contrasted and the condition of-workmanship ANT outline

LOW POWER CONSUMED MULTIPLIER DESIGN BY ANT ARCHITECTURE WITH FIXED WIDTH REPLICA REDUNDANCY BLOCK

In this paper, we propose a dependable low-control multiplier configuration by receiving algorithmic commotion tolerant (ANT) engineering with the settled width multiplier to assemble the lessened accuracy copy excess square (RPR). The proposed ANT engineering can take care of the demand of high accuracy, low power utilization, and zone proficiency. We plan the settled width RPR with mistake remuneration circuit by means of examining of likelihood and insights. Utilizing the halfway item terms of information remedy vector and minor info redress vector to bring down the truncation blunders, the equipment unpredictability of mistake pay circuit can be improved. In a 12 × 12 bit ANT multiplier, circuit zone in our settled width RPR can be brought down by 44.55% and control utilization in our ANT configuration can be spared by 23% as contrasted and the condition of-workmanship ANT outline

DESTINY: A Comprehensive Tool with 3D and Multi-Level Cell Memory Modeling Capability

To enable the design of large capacity memory structures, novel memory technologies such as non-volatile memory (NVM) and novel fabrication approaches, e.g., 3D stacking and multi-level cell (MLC) design have been explored. The existing modeling tools, however, cover only a few memory technologies, technology nodes and fabrication approaches. We present DESTINY, a tool for modeling 2D/3D memories designed using SRAM, resistive RAM (ReRAM), spin transfer torque RAM (STT-RAM), phase change RAM (PCM) and embedded DRAM (eDRAM) and 2D memories designed using spin orbit torque RAM (SOT-RAM), domain wall memory (DWM) and Flash memory. In addition to single-level cell (SLC) designs for all of these memories, DESTINY also supports modeling MLC designs for NVMs. We have extensively validated DESTINY against commercial and research prototypes of these memories. DESTINY is very useful for performing design-space exploration across several dimensions, such as optimizing for a target (e.g., latency, area or energy-delay product) for a given memory technology, choosing the suitable memory technology or fabrication method (i.e., 2D v/s 3D) for a given optimization target, etc. We believe that DESTINY will boost studies of next-generation memory architectures used in systems ranging from mobile devices to extreme-scale supercomputers. The latest source-code of DESTINY is available from the following git repository: https://bitbucket.org/sparsh_mittal/destiny_v2