A single MO-CFTA based electronically/temperature insensitive current-mode half-wave and full-wave rectifiers

The article presents a current-mode full-wave rectifier employing multiple output current follower transconductance amplifier (MO-CFTA). The both circuits description is very simple, it merely comprises only single MO-CFTA, without external passive element. In addition, the magnitude and direction of output currents can be controlled via electronically method. Furthermore, the outputs are independent of the thermal voltage (VT). The performances of the proposed circuits are investigated through PSpice. They show that the proposed circuits can function as a current-mode precision half-wave and full-wave rectifiers where input current range from 0uA to 514uA and -518uA to 518uA, respectively. They can be achieved at ±2V power supplies. The maximum power consumption is 3,01mW

[[alternative]]Design and IP Implementation of Low-Voltage Low-Power GHz PLL with BIST

計畫編號：NSC91-2215-E032-001研究期間：200208~200307研究經費：889,000[[sponsorship]]行政院國家科學委員

Design of multimedia processor based on metric computation

Media-processing applications, such as signal processing, 2D and 3D graphics rendering, and image compression, are the dominant workloads in many embedded systems today. The real-time constraints of those media applications have taxing demands on today's processor performances with low cost, low power and reduced design delay. To satisfy those challenges, a fast and efficient strategy consists in upgrading a low cost general purpose processor core. This approach is based on the personalization of a general RISC processor core according the target multimedia application requirements. Thus, if the extra cost is justified, the general purpose processor GPP core can be enforced with instruction level coprocessors, coarse grain dedicated hardware, ad hoc memories or new GPP cores. In this way the final design solution is tailored to the application requirements. The proposed approach is based on three main steps: the first one is the analysis of the targeted application using efficient metrics. The second step is the selection of the appropriate architecture template according to the first step results and recommendations. The third step is the architecture generation. This approach is experimented using various image and video algorithms showing its feasibility

Phase-shift interleaving control of variable-phase switched-capacitor converters

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Towards an on-chip boost switching power converter: a design space exploration

This work presents the design space exploration of a boost switching power converter focused on its monolithic implementation. An analysis in terms of the models of its main circuit elements (switching transistors, inductor, and capacitor) is described. The figure of merit is defined taking into account output voltage ripple, power efficiency, and occupied die area as performance indexes, from which a singular point that maximizes performance is obtained. Transistor-level simulation results for a particular 0.35 mm standard CMOS technology are presented to validate the approach.Peer ReviewedPostprint (published version

Error-resilient performance of Dirac video codec over packet-erasure channel

Video transmission over the wireless or wired network requires error-resilient mechanism since compressed video bitstreams are sensitive to transmission errors because of the use of predictive coding and variable length coding. This paper investigates the performance of a simple and low complexity error-resilient coding scheme which combines source and channel coding to protect compressed bitstream of wavelet-based Dirac video codec in the packet-erasure channel. By partitioning the wavelet transform coefficients of the motion-compensated residual frame into groups and independently processing each group using arithmetic and Forward Error Correction (FEC) coding, Dirac could achieves the robustness to transmission errors by giving the video quality which is gracefully decreasing over a range of packet loss rates up to 30% when compared with conventional FEC only methods. Simulation results also show that the proposed scheme using multiple partitions can achieve up to 10 dB PSNR gain over its existing un-partitioned format. This paper also investigates the error-resilient performance of the proposed scheme in comparison with H.264 over packet-erasure channel

Estimation of Autoregressive Parameters from Noisy Observations Using Iterated Covariance Updates

Estimating the parameters of the autoregressive (AR) random process is a problem that has been well-studied. In many applications, only noisy measurements of AR process are available. The effect of the additive noise is that the system can be modeled as an AR model with colored noise, even when the measurement noise is white, where the correlation matrix depends on the AR parameters. Because of the correlation, it is expedient to compute using multiple stacked observations. Performing a weighted least-squares estimation of the AR parameters using an inverse covariance weighting can provide significantly better parameter estimates, with improvement increasing with the stack depth. The estimation algorithm is essentially a vector RLS adaptive filter, with time-varying covariance matrix. Different ways of estimating the unknown covariance are presented, as well as a method to estimate the variances of the AR and observation noise. The notation is extended to vector autoregressive (VAR) processes. Simulation results demonstrate performance improvements in coefficient error and in spectrum estimation

A Power-Efficient Bio-Potential Acquisition Device with DS-MDE Sensors for Long-Term Healthcare Monitoring Applications

This work describes a power-efficient bio-potential acquisition device for long-term healthcare applications that is implemented using novel microelectromechanical dry electrodes (MDE) and a low power bio-potential processing chip. Using micromachining technology, an attempt is also made to enhance the sensing reliability and stability by fabricating a diamond-shaped MDE (DS-MDE) that has a satisfactory self-stability capability and superior electric conductivity when attached onto skin without any extra skin tissue injury technology. To acquire differential bio-potentials such as ECG signals, the proposed processing chip fabricated in a standard CMOS process has a high common mode rejection ratio (C.M.R.R.) differential amplifier and a 12-bit analog-to-digital converter (ADC). Use of the proposed system and integrate simple peripheral commercial devices can obtain the ECG signal efficiently without additional skin tissue injury and ensure continuous monitoring more than 70 hours with a 400 mAh battery