System-on-chip Computing and Interconnection Architectures for Telecommunications and Signal Processing

This dissertation proposes novel architectures and design techniques targeting SoC building blocks for telecommunications and signal processing applications. Hardware implementation of Low-Density Parity-Check decoders is approached at both the algorithmic and the architecture level. Low-Density Parity-Check codes are a promising coding scheme for future communication standards due to their outstanding error correction performance. This work proposes a methodology for analyzing effects of finite precision arithmetic on error correction performance and hardware complexity. The methodology is throughout employed for co-designing the decoder. First, a low-complexity check node based on the P-output decoding principle is designed and characterized on a CMOS standard-cells library. Results demonstrate implementation loss below 0.2 dB down to BER of 10^{-8} and a saving in complexity up to 59% with respect to other works in recent literature. High-throughput and low-latency issues are addressed with modified single-phase decoding schedules. A new "memory-aware" schedule is proposed requiring down to 20% of memory with respect to the traditional two-phase flooding decoding. Additionally, throughput is doubled and logic complexity reduced of 12%. These advantages are traded-off with error correction performance, thus making the solution attractive only for long codes, as those adopted in the DVB-S2 standard. The "layered decoding" principle is extended to those codes not specifically conceived for this technique. Proposed architectures exhibit complexity savings in the order of 40% for both area and power consumption figures, while implementation loss is smaller than 0.05 dB. Most modern communication standards employ Orthogonal Frequency Division Multiplexing as part of their physical layer. The core of OFDM is the Fast Fourier Transform and its inverse in charge of symbols (de)modulation. Requirements on throughput and energy efficiency call for FFT hardware implementation, while ubiquity of FFT suggests the design of parametric, re-configurable and re-usable IP hardware macrocells. In this context, this thesis describes an FFT/IFFT core compiler particularly suited for implementation of OFDM communication systems. The tool employs an accuracy-driven configuration engine which automatically profiles the internal arithmetic and generates a core with minimum operands bit-width and thus minimum circuit complexity. The engine performs a closed-loop optimization over three different internal arithmetic models (fixed-point, block floating-point and convergent block floating-point) using the numerical accuracy budget given by the user as a reference point. The flexibility and re-usability of the proposed macrocell are illustrated through several case studies which encompass all current state-of-the-art OFDM communications standards (WLAN, WMAN, xDSL, DVB-T/H, DAB and UWB). Implementations results are presented for two deep sub-micron standard-cells libraries (65 and 90 nm) and commercially available FPGA devices. Compared with other FFT core compilers, the proposed environment produces macrocells with lower circuit complexity and same system level performance (throughput, transform size and numerical accuracy). The final part of this dissertation focuses on the Network-on-Chip design paradigm whose goal is building scalable communication infrastructures connecting hundreds of core. A low-complexity link architecture for mesochronous on-chip communication is discussed. The link enables skew constraint looseness in the clock tree synthesis, frequency speed-up, power consumption reduction and faster back-end turnarounds. The proposed architecture reaches a maximum clock frequency of 1 GHz on 65 nm low-leakage CMOS standard-cells library. In a complex test case with a full-blown NoC infrastructure, the link overhead is only 3% of chip area and 0.5% of leakage power consumption. Finally, a new methodology, named metacoding, is proposed. Metacoding generates correct-by-construction technology independent RTL codebases for NoC building blocks. The RTL coding phase is abstracted and modeled with an Object Oriented framework, integrated within a commercial tool for IP packaging (Synopsys CoreTools suite). Compared with traditional coding styles based on pre-processor directives, metacoding produces 65% smaller codebases and reduces the configurations to verify up to three orders of magnitude

Baseband analog front-end and digital back-end for reconfigurable multi-standard terminals

Multimedia applications are driving wireless network operators to add high-speed data services such as Edge (E-GPRS), WCDMA (UMTS) and WLAN (IEEE 802.11a,b,g) to the existing GSM network. This creates the need for multi-mode cellular handsets that support a wide range of communication standards, each with a different RF frequency, signal bandwidth, modulation scheme etc. This in turn generates several design challenges for the analog and digital building blocks of the physical layer. In addition to the above-mentioned protocols, mobile devices often include Bluetooth, GPS, FM-radio and TV services that can work concurrently with data and voice communication. Multi-mode, multi-band, and multi-standard mobile terminals must satisfy all these different requirements. Sharing and/or switching transceiver building blocks in these handsets is mandatory in order to extend battery life and/or reduce cost. Only adaptive circuits that are able to reconfigure themselves within the handover time can meet the design requirements of a single receiver or transmitter covering all the different standards while ensuring seamless inter-interoperability. This paper presents analog and digital base-band circuits that are able to support GSM (with Edge), WCDMA (UMTS), WLAN and Bluetooth using reconfigurable building blocks. The blocks can trade off power consumption for performance on the fly, depending on the standard to be supported and the required QoS (Quality of Service) leve

IST-2000-30148 I-METRA: D3.1 Design, analysis and selection of suitable algorithms

This deliverable contains a description of the space-time coding algorithms to be simulated within the I-METRA project. Different families of algorithms have been selected and described in this document with the objective of evaluating their performance. One of the main objectives of the I-METRA project is to impact into the current standardisation efforts related to the introduction of Multiple Input Multiple Output (MIMO) configurations into the High Speed Downlink and Uplink Packet Access concepts of UMTS (HSDPA and HSUPA). This required a review of the current specifications for these systems and the analysis of the impact of the potential incorporation of the selected MIMO schemes.Preprin

System capacity enhancement for 5G network and beyond

A thesis submitted to the University of Bedfordshire, in fulfilment of the requirements for the degree of Doctor of PhilosophyThe demand for wireless digital data is dramatically increasing year over year. Wireless communication systems like Laptops, Smart phones, Tablets, Smart watch, Virtual Reality devices and so on are becoming an important part of people’s daily life. The number of mobile devices is increasing at a very fast speed as well as the requirements for mobile devices such as super high-resolution image/video, fast download speed, very short latency and high reliability, which raise challenges to the existing wireless communication networks. Unlike the previous four generation communication networks, the fifth-generation (5G) wireless communication network includes many technologies such as millimetre-wave communication, massive multiple-input multiple-output (MIMO), visual light communication (VLC), heterogeneous network (HetNet) and so forth. Although 5G has not been standardised yet, these above technologies have been studied in both academia and industry and the goal of the research is to enhance and improve the system capacity for 5G networks and beyond by studying some key problems and providing some effective solutions existing in the above technologies from system implementation and hardware impairments’ perspective. The key problems studied in this thesis include interference cancellation in HetNet, impairments calibration for massive MIMO, channel state estimation for VLC, and low latency parallel Turbo decoding technique. Firstly, inter-cell interference in HetNet is studied and a cell specific reference signal (CRS) interference cancellation method is proposed to mitigate the performance degrade in enhanced inter-cell interference coordination (eICIC). This method takes carrier frequency offset (CFO) and timing offset (TO) of the user’s received signal into account. By reconstructing the interfering signal and cancelling it afterwards, the capacity of HetNet is enhanced. Secondly, for massive MIMO systems, the radio frequency (RF) impairments of the hardware will degrade the beamforming performance. When operated in time duplex division (TDD) mode, a massive MIMO system relies on the reciprocity of the channel which can be broken by the transmitter and receiver RF impairments. Impairments calibration has been studied and a closed-loop reciprocity calibration method is proposed in this thesis. A test device (TD) is introduced in this calibration method that can estimate the transmitters’ impairments over-the-air and feed the results back to the base station via the Internet. The uplink pilots sent by the TD can assist the BS receivers’ impairment estimation. With both the uplink and downlink impairments estimates, the reciprocity calibration coefficients can be obtained. By computer simulation and lab experiment, the performance of the proposed method is evaluated. Channel coding is an essential part of a wireless communication system which helps fight with noise and get correct information delivery. Turbo codes is one of the most reliable codes that has been used in many standards such as WiMAX and LTE. However, the decoding process of turbo codes is time-consuming and the decoding latency should be improved to meet the requirement of the future network. A reverse interleave address generator is proposed that can reduce the decoding time and a low latency parallel turbo decoder has been implemented on a FPGA platform. The simulation and experiment results prove the effectiveness of the address generator and show that there is a trade-off between latency and throughput with a limited hardware resource. Apart from the above contributions, this thesis also investigated multi-user precoding for MIMO VLC systems. As a green and secure technology, VLC is achieving more and more attention and could become a part of 5G network especially for indoor communication. For indoor scenario, the MIMO VLC channel could be easily ill-conditioned. Hence, it is important to study the impact of the channel state to the precoding performance. A channel state estimation method is proposed based on the signal to interference noise ratio (SINR) of the users’ received signal. Simulation results show that it can enhance the capacity of the indoor MIMO VLC system

Link level performance evaluation and link abstraction for LTE/LTE-advanced downlink

Els objectius principals d'aquesta tesis són l'avaluació del rendiment a nivell d'enllaç i l'estudi de l'abstracció de l'enllaç pel LTE/LTE-Advanced DL. S’ha desenvolupat un simulador del nivell d'enllaç E-UTRA DL basat en la tecnologia MIMO-OFDM. Es simulen els errors d'estimació de canal amb un model d'error de soroll additiu Gaussià anomenat CEEM. El resultat d'aquest simulador serveix per avaluar el rendiment a nivell d'enllaç del LTE/LTE-Advanced DL en diferents entorns . La idea bàsica dels mètodes d'abstracció de l'enllaç és mapejar el vector de SNRs de les subportadores a un valor escalar, l'anomenada ESNR, la qual és usada per a predir la BLER. Proposem un innovador mètode d'abstracció de l'enllaç que pot predir la BLER amb bona precisió en esvaïments multicamí i que inclouen els efectes de les retransmissions HARQ. El mètode proposat es basa amb l'estimació de la informació mútua entre els bits transmesos i els LLRs rebuts.The main objectives of this dissertation are the evaluation of the link level performance and the study of link abstraction for LTE/LTE-Advanced DL. An E-UTRA DL link level simulator has been developed based on MIMO-OFDM technology. We simulate channel estimation errors by a Gaussian additive noise error model called CEEM. The result of this simulator serves to evaluate the MIMO-OFDM LTE/LTE-Advanced DL link level performance in different environments. The basic idea of link abstraction methods is to map the vector of the subcarrier SNRs to a single scalar, the ESNR, which is then used to predict the BLER. We propose a novel link abstraction method that can predict the BLER with good accuracy in multipath fading and including the effects of HARQ retransmissions. The proposed method is based on estimating the mutual information between the transmitted bits and the received LLRs.Postprint (published version

Flux observer algorithms for direct torque control of brushless doubly-fed reluctance machines

Direct Torque Control (DTC) has been extensively researched and applied to most AC machines during the last two decades. Its first application to the Brushless Doubly-Fed Reluctance Machine (BDFRM), a promising cost-effective candidate for drive and generator systems with limited variable speed ranges (such as large pumps or wind turbines), has only been reported a few years ago. However, the original DTC scheme has experienced flux estimation problems and compromised performance under the maximum torque per inverter ampere (MTPIA) conditions. This deficiency at low current and torque levels may be overcome and much higher accuracy achieved by alternative estimation approaches discussed in this paper using Kalman Filter (KF) and/or Sliding Mode Observer (SMO). Computer simulations accounting for real-time constraints (e.g. measurement noise, transducer DC offset etc.) have produced realistic results similar to those one would expect from an experimental setup

Power control for WCDMA

This project tries to introduce itself in the physical implementations that make possible the denominated third generation mobile technology. As well as to know the technology kind that makes possible, for example, a video-call in real time. During this project, the different phases passed from the election of WCDMA like the access method for UMTS will appear. Its coexistence with previous network GSM will be analyzed, where the compatibility between systems has been one of the most important aspects in the development of WCDMA, the involved standardization organisms in the process, as well as the different protocols that make the mobile communications within a network UTRAN possible. Special emphasis during the study of the great contribution that has offered WCDMA with respect to the control of power of the existing signals will be made. The future lines that are considered in the present, and other comment that already are in their last phase of development in the field of the mobile technology. UMTS through WCDMA can be summarized like a revolution of the air interface accompanied by a revolution in the network of their architecture

Structural and functional analysis of the middle segment of hsp90: implications for ATP hydrolysis and client protein and cochaperone interactions

Activation of client proteins by the Hsp90 molecular chaperone is dependent on binding and hydrolysis of ATP, which drives a molecular clamp via transient dimerization of the N-terminal domains. The crystal structure of the middle segment of yeast Hsp90 reveals considerable evolutionary divergence from the equivalent regions of other GHKL protein family members such as MutL and GyrB, including an additional domain of new fold. Using the known structure of the N-terminal nucleotide binding domain, a model for the Hsp90 dimer has been constructed. From this structure, residues implicated in the ATPase-coupled conformational cycle and in interactions with client proteins and the activating cochaperone Aha1 have been identified, and their roles functionally characterized in vitro and in vivo