Dynamics of reconfigurable artificial spin ice: toward magnonic functional materials

Over the past few years, the study of magnetization dynamics in artificial spin ices has become a vibrant field of study. Artificial spin ices are ensembles of geometrically arranged, interacting magnetic nanoislands, which display frustration by design. These were initially created to mimic the behavior in rare earth pyrochlore materials and to study emergent behavior and frustration using two-dimensional magnetic measurement techniques. Recently, it has become clear that it is possible to create artificial spin ices, which can potentially be used as functional materials. In this perspective, we review the resonant behavior of spin ices in the GHz frequency range, focusing on their potential application as magnonic crystals. In magnonic crystals, spin waves are functionalized for logic applications by means of band structure engineering. While it has been established that artificial spin ices can possess rich mode spectra, the applicability of spin ices to create magnonic crystals hinges upon their reconfigurability. Consequently, we describe recent work aiming to develop techniques and create geometries allowing full reconfigurability of the spin ice magnetic state. We also discuss experimental, theoretical, and numerical methods for determining the spectral response of artificial spin ices and give an outlook on new directions for reconfigurable spin ices

Design Automation and Application for Emerging Reconfigurable Nanotechnologies

In the last few decades, two major phenomena have revolutionized the electronic industry – the ever-increasing dependence on electronic circuits and the Complementary Metal Oxide Semiconductor (CMOS) downscaling. These two phenomena have been complementing each other in a way that while electronics, in general, have demanded more computations per functional unit, CMOS downscaling has aptly supported such needs. However, while the computational demand is still rising exponentially, CMOS downscaling is reaching its physical limits. Hence, the need to explore viable emerging nanotechnologies is more imperative than ever. This thesis focuses on streamlining the existing design automation techniques for a class of emerging reconfigurable nanotechnologies. Transistors based on this technology exhibit duality in conduction, i.e. they can be configured dynamically either as a p-type or an n-type device on the application of an external bias. Owing to this dynamic reconfiguration, these transistors are also referred to as Reconfigurable Field-Effect Transistors (RFETs). Exploring and developing new technologies just like CMOS, require tackling two main challenges – first, design automation flow has to be modified to enable tailor- made circuit designs. Second, possible application opportunities should be explored where such technologies can outsmart the existing CMOS technologies. This thesis targets the above two objectives for emerging reconfigurable nanotechnologies by proposing approaches for enabling an Electronic Design Automation (EDA) flow for circuits based on RFETs and exploring hardware security as an application that exploits the transistor-level dynamic reconfiguration offered by this technology. This thesis explains the bottom-up approach adopted to propose a logic synthesis flow by identifying new logic gates and circuit design paradigms that can particularly exploit the dynamic reconfiguration offered by these novel nanotechnologies. This led to the subsequent need of finding natural Boolean logic abstraction for emerging reconfigurable nanotechnologies as it is shown that the existing abstraction of negative unate logic for CMOS technologies is sub-optimal for RFETs-based circuits. In this direction, it has been shown that duality in Boolean logic is a natural abstraction for this technology and can truly represent the duality in conduction offered by individual transistors. Finding this abstraction paved the way for defining suitable primitives and proposing various algorithms for logic synthesis and technology mapping. The following step is to explore compatible physical synthesis flow for emerging reconfigurable nanotechnologies. Using silicon nanowire-based RFETs, .lef and .lib files have been provided which can provide an end-to-end flow to generate .GDSII file for circuits exclusively based on RFETs. Additionally, new approaches have been explored to improve placement and routing for circuits based on reconfigurable nanotechnologies. It has been demonstrated how these approaches led to superior results as compared to the native flow meant for CMOS. Lastly, the unique property of transistor-level reconfiguration offered by RFETs is utilized to implement efficient Intellectual Property (IP) protection schemes against adversarial attacks. The ability to control the conduction of individual transistors can be argued as one of the impactful features of this technology and suitably fits into the paradigm of security measures. Prior security schemes based on CMOS technology often come with large overheads in terms of area, power, and delay. In contrast, RFETs-based hardware security measures such as logic locking, split manufacturing, etc. proposed in this thesis, demonstrate affordable security solutions with low overheads. Overall, this thesis lays a strong foundation for the two main objectives – design automation, and hardware security as an application, to push emerging reconfigurable nanotechnologies for commercial integration. Additionally, contributions done in this thesis are made available under open-source licenses so as to foster new research directions and collaborations.:Abstract List of Figures List of Tables 1 Introduction 1.1 What are emerging reconfigurable nanotechnologies? 1.2 Why does this technology look so promising? 1.3 Electronics Design Automation 1.4 The game of see-saw: key challenges vs benefits for emerging reconfigurable nanotechnologies 1.4.1 Abstracting ambipolarity in logic gate designs 1.4.2 Enabling electronic design automation for RFETs 1.4.3 Enhanced functionality: a suitable fit for hardware security applications 1.5 Research questions 1.6 Entire RFET-centric EDA Flow 1.7 Key Contributions and Thesis Organization 2 Preliminaries 2.1 Reconfigurable Nanotechnology 2.1.1 1D devices 2.1.2 2D devices 2.1.3 Factors favoring circuit-flexibility 2.2 Feasibility aspects of RFET technology 2.3 Logic Synthesis Preliminaries 2.3.1 Circuit Model 2.3.2 Boolean Algebra 2.3.3 Monotone Function and the property of Unateness 2.3.4 Logic Representations 3 Exploring Circuit Design Topologies for RFETs 3.1 Contributions 3.2 Organization 3.3 Related Works 3.4 Exploring design topologies for combinational circuits: functionality-enhanced logic gates 3.4.1 List of Combinational Functionality-Enhanced Logic Gates based on RFETs 3.4.2 Estimation of gate delay using the logical effort theory 3.5 Invariable design of Inverters 3.6 Sequential Circuits 3.6.1 Dual edge-triggered TSPC-based D-flip flop 3.6.2 Exploiting RFET’s ambipolarity for metastability 3.7 Evaluations 3.7.1 Evaluation of combinational logic gates 3.7.2 Novel design of 1-bit ALU 3.7.3 Comparison of the sequential circuit with an equivalent CMOS-based design 3.8 Concluding remarks 4 Standard Cells and Technology Mapping 4.1 Contributions 4.2 Organization 4.3 Related Work 4.4 Standard cells based on RFETs 4.4.1 Interchangeable Pull-Up and Pull-Down Networks 4.4.2 Reconfigurable Truth-Table 4.5 Distilling standard cells 4.6 HOF-based Technology Mapping Flow for RFETs-based circuits 4.6.1 Area adjustments through inverter sharings 4.6.2 Technology Mapping Flow 4.6.3 Realizing Parameters For The Generic Library 4.6.4 Defining RFETs-based Genlib for HOF-based mapping 4.7 Experiments 4.7.1 Experiment 1: Distilling standard-cells from a benchmark suite 4.7.2 Experiment 2A: HOF-based mapping . 4.7.3 Experiment 2B: Using the distilled standard-cells during mapping 4.8 Concluding Remarks 5 Logic Synthesis with XOR-Majority Graphs 5.1 Contributions 5.2 Organization 5.3 Motivation 5.4 Background and Preliminaries 5.4.1 Terminologies 5.4.2 Self-duality in NPN classes 5.4.3 Majority logic synthesis 5.4.4 Earlier work on XMG 5.4.5 Classification of Boolean functions 5.5 Preserving Self-Duality 5.5.1 During logic synthesis 5.5.2 During versatile technology mapping 5.6 Advanced Logic synthesis techniques 5.6.1 XMG resubstitution 5.6.2 Exact XMG rewriting 5.7 Logic representation-agnostic Mapping 5.7.1 Versatile Mapper 5.7.2 Support of supergates 5.8 Creating Self-dual Benchmarks 5.9 Experiments 5.9.1 XMG-based Flow 5.9.2 Experimental Setup 5.9.3 Synthetic self-dual benchmarks 5.9.4 Cryptographic benchmark suite 5.10 Concluding remarks and future research directions 6 Physical synthesis flow and liberty generation 6.1 Contributions 6.2 Organization 6.3 Background and Related Work 6.3.1 Related Works 6.3.2 Motivation 6.4 Silicon Nanowire Reconfigurable Transistors 6.5 Layouts for Logic Gates 6.5.1 Layouts for Static Functional Logic Gates 6.5.2 Layout for Reconfigurable Logic Gate 6.6 Table Model for Silicon Nanowire RFETs 6.7 Exploring Approaches for Physical Synthesis 6.7.1 Using the Standard Place & Route Flow 6.7.2 Open-source Flow 6.7.3 Concept of Driver Cells 6.7.4 Native Approach 6.7.5 Island-based Approach 6.7.6 Utilization Factor 6.7.7 Placement of the Island on the Chip 6.8 Experiments 6.8.1 Preliminary comparison with CMOS technology 6.8.2 Evaluating different physical synthesis approaches 6.9 Results and discussions 6.9.1 Parameters Which Affect The Area 6.9.2 Use of Germanium Nanowires Channels 6.10 Concluding Remarks 7 Polymporphic Primitives for Hardware Security 7.1 Contributions 7.2 Organization 7.3 The Shift To Explore Emerging Technologies For Security 7.4 Background 7.4.1 IP protection schemes 7.4.2 Preliminaries 7.5 Security Promises 7.5.1 RFETs for logic locking (transistor-level locking) 7.5.2 RFETs for split manufacturing 7.6 Security Vulnerabilities 7.6.1 Realization of short-circuit and open-circuit scenarios in an RFET-based inverter 7.6.2 Circuit evaluation on sub-circuits 7.6.3 Reliability concerns: A consequence of short-circuit scenario 7.6.4 Implication of the proposed security vulnerability 7.7 Analytical Evaluation 7.7.1 Investigating the security promises 7.7.2 Investigating the security vulnerabilities 7.8 Concluding remarks and future research directions 8 Conclusion 8.1 Concluding Remarks 8.2 Directions for Future Work Appendices A Distilling standard-cells B RFETs-based Genlib C Layout Extraction File (.lef) for Silicon Nanowire-based RFET D Liberty (.lib) file for Silicon Nanowire-based RFET

Modèle de placement pour les architectures nano-composantes

RÉSUMÉ Depuis la création de l’industrie des transistors CMOS, on assiste à un développement sans précédent de la miniaturisation. L’ITRS prévoit la limite des technologies basées sur le CMOS en 2020. Dans ce contexte, apparait de nouvelles disciplines, au coeur de la nanotechnologie, qui permettent de définir de nouvelles technologies permettant de compléter et/ou remplacer les transistors CMOS. Ces nouveaux transistors ouvrent la voie vers un nouveau paradigme d’architectures nano-composantes. Ces architectures ont trois principales caractéristiques : Les cellules logiques sont dynamiquement reconfigurables. Ce qui donne la possibilité d’exécuter en pipeline plusieurs fonctions différentes; La granularité est très fine. Ceci impose de considérer l’extensibilité des outils qui permettront l’exploitation de ces architectures; Elles ont une structure hiérarchique particulière : Dans les architectures nano-composantes les cellules logiques sont organisées en matrices avec des connexions statiques et les matrices en réseau de matrices avec des connexions dynamiques. Ces architectures peuvent alors être paramétrées en fonction de la taille des matrices (nombre de cellules) et de la taille du réseau (nombre de matrices). Pour prouver l’efficacité des architectures nano-composantes, il va falloir envisager la réalisation physique de systèmes complexes très performants basés sur ces technologies ainsi que l’utilisation des ces nano-systèmes. Comme l’accès au prototypage est très difficile et qu’il est souhaitable de réduire le temps de production des systèmes, la définition de nouveaux outils de conception assistée par ordinateur (CAO) s’avère nécessaire. Plusieurs outils CAO permettant la définition de systèmes basés sur les architectures conventionnelles existent. Cependant, ces outils ne prennent pas en compte les caractéristiques des architectures nano-composantes.----------ABSTRACT International Technology Roadmap for Semiconductors (ITRS) predicts that CMOS devices will reach their limits in 2022. Consequently, new devices and more efficient technologies are required. In this context, many efforts have been made to extend or replace conventional, CMOS devices. Some devices based on Field Effect Transistor (FET) nanotechnology such as the Dual Gate Carbon NanoTube FET (DG-CNTFET), the Nano Wire FET (NWFET) or the Grapheme FET (GFET) are promising candidates to replace CMOS devices. They lead to define new paradigm of non-conventional architectures (so called nano-component architecture). Nano-component architectures have three main characteristics: The logic cells are dynamically reconfigurable. This characteristic allows performing pipeline on several different functions; The granularity is ultra-fine (at most 2-bit operation). This characteristic implies to take into consideration scalability to exploit those architectures; The logic cells are organized with hierarchical structure and connectivity restrictions. In this structure, cells are organized in matrix and the matrices are organized in cluster. Exploiting those characteristics, nano–architecture are expected, compared to conventional architectures, to reduce the area and the cost and to improve the performance of a broad range of applications. In order to explore the potential of nano-architecture, new CAD tools are required. Those tools must take into account many parameters in nano-architecture definition: the number of cell in matrices, the number of matrices in cluster, the hierarchical structure, the connectivity restrictions, the fine granularity, the high reconfiguration, the pipeline and parallel execution… Although many CAD tools defined for conventional architecture have been proposed, they do not take into consideration nano-architecture parameters

Recent Advances in Embedded Computing, Intelligence and Applications

The latest proliferation of Internet of Things deployments and edge computing combined with artificial intelligence has led to new exciting application scenarios, where embedded digital devices are essential enablers. Moreover, new powerful and efficient devices are appearing to cope with workloads formerly reserved for the cloud, such as deep learning. These devices allow processing close to where data are generated, avoiding bottlenecks due to communication limitations. The efficient integration of hardware, software and artificial intelligence capabilities deployed in real sensing contexts empowers the edge intelligence paradigm, which will ultimately contribute to the fostering of the offloading processing functionalities to the edge. In this Special Issue, researchers have contributed nine peer-reviewed papers covering a wide range of topics in the area of edge intelligence. Among them are hardware-accelerated implementations of deep neural networks, IoT platforms for extreme edge computing, neuro-evolvable and neuromorphic machine learning, and embedded recommender systems

On Fault Tolerance Methods for Networks-on-Chip

Technology scaling has proceeded into dimensions in which the reliability of manufactured devices is becoming endangered. The reliability decrease is a consequence of physical limitations, relative increase of variations, and decreasing noise margins, among others. A promising solution for bringing the reliability of circuits back to a desired level is the use of design methods which introduce tolerance against possible faults in an integrated circuit. This thesis studies and presents fault tolerance methods for network-onchip (NoC) which is a design paradigm targeted for very large systems-onchip. In a NoC resources, such as processors and memories, are connected to a communication network; comparable to the Internet. Fault tolerance in such a system can be achieved at many abstraction levels. The thesis studies the origin of faults in modern technologies and explains the classification to transient, intermittent and permanent faults. A survey of fault tolerance methods is presented to demonstrate the diversity of available methods. Networks-on-chip are approached by exploring their main design choices: the selection of a topology, routing protocol, and flow control method. Fault tolerance methods for NoCs are studied at different layers of the OSI reference model. The data link layer provides a reliable communication link over a physical channel. Error control coding is an efficient fault tolerance method especially against transient faults at this abstraction level. Error control coding methods suitable for on-chip communication are studied and their implementations presented. Error control coding loses its effectiveness in the presence of intermittent and permanent faults. Therefore, other solutions against them are presented. The introduction of spare wires and split transmissions are shown to provide good tolerance against intermittent and permanent errors and their combination to error control coding is illustrated. At the network layer positioned above the data link layer, fault tolerance can be achieved with the design of fault tolerant network topologies and routing algorithms. Both of these approaches are presented in the thesis together with realizations in the both categories. The thesis concludes that an optimal fault tolerance solution contains carefully co-designed elements from different abstraction levelsSiirretty Doriast

Fabrication, Mechanical Characterization, and Modeling of 3D Architected Materials upon Static and Dynamic Loading

Architected materials have been ubiquitous in nature, enabling unique properties that are unachievable by monolithic, homogeneous materials. Inspired by natural processes, man-made three-dimensional (3D) architected materials have been reported to enable novel mechanical properties such as high stiffness- and strength-to-density ratios, extreme resilience, or high energy absorption. Furthermore, advanced fabrication techniques have enabled architected materials with feature sizes at the nanometer-scale, which exploit material size effects to approach theoretical bounds. However, most architected materials have relied on symmetry, periodicity, and lack of defects to achieve the desired mechanical response, resulting in sub-optimal mechanical response under the presence of inevitable defects. Additionally, most of these nano- and micro-architected materials have only been studied in the static regime, leaving the dynamic parameter space unexplored. In this work, we address these issues by: (i) proposing numerical and theoretical tools that predict the behavior of architected materials with non-ideal geometries, (ii) presenting a pathway for scalable fabrication of tunable nano-architected materials, and (iii) exploring the response of nano- and micro-architected materials under three types of dynamic loading. We first explore lattice architectures with features at the micro- and millimeter scales and provide an extension to the classical stiffness scaling laws, enabled by reduced-order numerical models and experiments at both scales. After discussing the effect of nodes (i.e., junctions) on the mechanical response of lattice architectures, we propose alternative node-less geometries that eliminate the stress concentrations associated with nodes to provide extreme resilience. Using natural processes such as spinodal decomposition, we present pathways to fabricate a version of these materials with samples sizes on the order of cubic centimeters while achieving feature sizes on the order of tens of nanometers. In the dynamic regime, we design, fabricate, and test micro-architected materials with tunable vibrational band gaps through the use of architectural reconfiguration and local resonance. Lastly, we present methods to fabricate carbon-based materials at the nano- and centimeter scales and test them under supersonic impact and blast conditions, respectively. Our work provides explorations into pathways that could enable the use of nano- and micro-architected materials for applications that go beyond small-volume, quasi-static mechanical regimes.</p