Solid State Circuits Technologies

The evolution of solid-state circuit technology has a long history within a relatively short period of time. This technology has lead to the modern information society that connects us and tools, a large market, and many types of products and applications. The solid-state circuit technology continuously evolves via breakthroughs and improvements every year. This book is devoted to review and present novel approaches for some of the main issues involved in this exciting and vigorous technology. The book is composed of 22 chapters, written by authors coming from 30 different institutions located in 12 different countries throughout the Americas, Asia and Europe. Thus, reflecting the wide international contribution to the book. The broad range of subjects presented in the book offers a general overview of the main issues in modern solid-state circuit technology. Furthermore, the book offers an in depth analysis on specific subjects for specialists. We believe the book is of great scientific and educational value for many readers. I am profoundly indebted to the support provided by all of those involved in the work. First and foremost I would like to acknowledge and thank the authors who worked hard and generously agreed to share their results and knowledge. Second I would like to express my gratitude to the Intech team that invited me to edit the book and give me their full support and a fruitful experience while working together to combine this book

Cu Wiring Fabrication by Supercritical Fluid Deposition for MEMS Devices

Process technologies that use supercritical CO2 fluids to fabricate high-aspect-ratio three-dimensional nano- and micro-components are described. Supercritical CO2 is a state of CO2 above the critical point. Supercritical CO2 fluids are used as alternatives to common media (gases and liquids) in MEMS device fabrication to both overcome the drawbacks of these materials and to realize a superior three-dimensional process opportunity. Supercritical fluids behave as both gases and liquids, offer many of the advantages of both, and have zero surface tension. Supercritical fluids are an ideal medium for fabricating very high-aspect-ratio features owing to their superior capability of diffusion transport. As MEMSs have complex and high-aspect-ratio structures, using a supercritical fluid as a process medium in MEMS fabrication provides ideal performance in film coating, plug filling of concave features, and the etching/cleaning of residues. In this chapter, the physicochemical properties of supercritical fluids are first described in terms of MEMS processing, but from a different point of view than that of the common literature on supercritical chemical processing. Next, various applications to thin film processing are described with a focus on interconnect/wiring fabrication of MEMS devices

3D modeling and integration of current and future interconnect technologies

Title from PDF of title page viewed June 21, 2021Dissertation advisor: Masud H. ChowdhuryVitaIncludes bibliographical references (pages 133-138)Thesis (Ph.D.)--School of Computing and Engineering and Department of Physics and Astronomy. University of Missouri--Kansas City, 2021To ensure maximum circuit reliability it is very important to estimate the circuit performance and signal integrity in the circuit design phase. A full phase simulation for performance estimation of a large-scale circuit not only require a massive computational resource but also need a lot of time to produce acceptable results. The estimation of performance/signal integrity of sub-nanometer circuits mostly depends on the interconnect capacitance. So, an accurate model for interconnect capacitance can be used in the circuit CAD (computer-aided design) tools for circuit performance estimation before circuit fabrication which reduces the computational resource requirement as well as the time constraints. We propose a new capacitance models for interconnect lines in multilevel interconnect structures by geometrically modeling the electrical flux lines of the interconnect lines. Closed-form equations have been derived analytically for ground and coupling capacitance. First, the capacitance model for a single line is developed, and then the new model is used to derive expressions for the capacitance of a line surrounded by neighboring lines in the same and the adjacent layers above and below. These expressions are simple, and the calculated results are within 10% of Ansys Q3D extracted values. Through silicon via (TSV) is one of the key components of the emerging 3D ICs. However, increasing number of TSVs in smaller silicon area leads to some severe negative impacts on the performance of the 3D IC. Growing signal integrity issues in TSVs is one of the major challenges of 3D integration. In this paper, different materials for the cores of the vias and the interposers are investigated to find the best possible combination that can reduce crosstalk and other losses like return loss and insertion loss in the TSVs. We have explored glass and silicon as interposer materials. The simulation results indicate that glass is the best option as interposer material although silicon interposer has some distinct advantages. For via cores three materials - copper (Cu), tungsten (W) and Cu-W bimetal are considered. From the analysis it can concluded that W would be better for high frequency applications due to lower transmission coefficient. Cu offers higher conductivity, but it has larger thermal expansion coefficient mismatch with silicon. The performance of Cu-W bimetal via would be in between Cu and W. However, W has a thermal expansion coefficient close to silicon. Therefore, bimetal Cu-W based TSV with W as the outer layer would be a suitable option for high frequency 3D IC. Here, we performed the analysis in terms of return loss, transmission coefficient and crosstalk in the vias. Signal speed in current digital systems depends mainly on the delay of interconnects. To overcome this delay problem and keep up with Moore’s law, 3D integrated circuit (vertical integration of multiple dies) with through-silicon via (TSV) has been introduced to ensure much smaller interconnect lengths, and lower delay and power consumption compared to conventional 2D IC technology. Like 2D circuit, the estimation of 3D circuit performance depends on different electrical parameters (capacitance, resistance, inductance) of the TSV. So, accurate modeling of the electrical parameters of the TSV is essential for the design and analysis of 3D ICs. We propose a set of new models to estimate the capacitance, resistance, and inductance of a Cu-filled TSV. The proposed analytical models are derived from the physical shape and the size of the TSV. The modeling approach is comprehensive and includes both the cylindrical and tapered TSVs as well as the bumps. On-chip integration of inductors has always been very challenging. However, for sub- 14nm on-chip applications, large area overhead imposed by the on-chip capacitors and inductors has become a more severe concern. To overcome this issue and ensure power integrity, a novel 3D Through-Silicon-Via (TSV) based inductor design is presented. The proposed TSV based inductor has the potential to achieve both high density and high performance. A new design of a Voltage Controlled Oscillator (VCO) utilizing the TSV based inductor is also presented. The implementation of the VCO is intended to study the feasibility, performance, and real-world application of the proposed TSV based inductor.Introduction -- Background of capacitance modeling of on-chip interconnect -- Accurate modeling of interconnect capacitance in multilevel interconnect structures for sub 22nm technology -- Analysis of different materials and structures for through silicon via and through glass via in 3D integrated circuits -- Impacts of different shapes of through-silicon-via core on 3D IC performance -- Accurate electrical modeling of cu-filled through-silicon-via (TSV) -- Design and characterize TSV based inductor for high frequency voltage-controlled oscillator design -- Conclusion and future wor

Carbon Nanotubes Based 3-D Matrix for Enabling Three-Dimensional Nano-Magneto-Electronics

This letter describes the use of vertically aligned carbon nanotubes (CNT)-based arrays with estimated 2-nm thick cobalt (Co) nanoparticles deposited inside individual tubes to unravel the possibility of using the unique templates for ultra-high-density low-energy 3-D nano-magneto-electronic devices. The presence of oriented 2-nm thick Co layers within individual nanotubes in the CNT-based 3-D matrix is confirmed through VSM measurements as well as an energy-dispersive X-ray spectroscopy (EDS)