GaN Power Devices: Discerning Application-Specific Challenges and Limitations in HEMTs

GaN power devices are typically used in the 600 V market, for high efficiency, high power-density systems. For these devices, the lateral optimization of gate-to-drain, gate, and gate-to-source lengths, as well as gate field-plate length are critical for optimizing breakdown voltage and performance. This work presents a systematic study of lateral scaling optimization for high voltage devices to minimize figure of merit and maximize breakdown voltage. In addition, this optimization is extended for low voltage devices ( \u3c 100 V), presenting results to optimize both lateral features and vertical features. For low voltage design, simulation work suggests that breakdown is more reliant on punch-through as the primary breakdown mechanism rather than on vertical leakage current as is the case with high-voltage devices. A fabrication process flow has been developed for fabricating Schottky-gate, and MIS-HEMT structures at UCF in the CREOL cleanroom. The fabricated devices were designed to validate the simulation work for low voltage GaN devices. The UCF fabrication process is done with a four layer mask, and consists of mesa isolation, ohmic recess etch, an optional gate insulator layer, ohmic metallization, and gate metallization. Following this work, the fabrication process was transferred to the National Nano Device Laboratories (NDL) in Hsinchu, Taiwan, to take advantage of the more advanced facilities there. Following fabrication, a study has been performed on defect induced performance degradation, leading to the observation of a new phenomenon: trap induced negative differential conductance (NDC). Typically NDC is caused by self-heating, however by implementing a substrate bias test in conjunction with pulsed I-V testing, the NDC seen in our fabricated devices has been confirmed to be from buffer traps that are a result of poor channel carrier confinement during the dc operating condition

Analysis of drain current saturation behaviour in GaN polarisation super junction HFETs

The magnitude of saturation current in a power device significantly impacts its short-circuit capability. In conjunction with the unprecedented miniaturisation that gallium nitride (GaN) offers, there is a compelling rationale to examine this critical parameter in GaN transistors for thermally stable and reliable power converter applications. This study presents a comprehensive analysis of the physical behaviour that yields intrinsically low drain current saturation in GaN polarisation super junction heterojunction field-effect transistors (PSJ HFETs). The analysis in this work has been performed using electrical characterisation data of conventional and PSJ HFETs, supported by physics-based two-dimensional device simulations. Insight is gained on the differing device architecture-dependent mechanisms that determine the magnitude of drain current density in both types of devices when biased in the saturation region

Improvement of Breakdown Characteristics in AlGaN/GaN Power HEMTs

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2013. 8. 한민구.Gallium Nitride (GaN) based high electron mobility transistor (HEMT) or heterostructure field effect transistor (HFET) are promising device for high-power switches which has to operate in electrically and environmentally harsh condition. The devices benefits from the material properties GaN offers: high critical field, high carrier mobility and a high saturation velocity of carriers. The breakdown voltage in AlGaN/GaN HEMTs is known to be triggered by gate leakage caused by the concentration of the electrical field at the drain-side edge of the gate electrode. The influence of gate leakage on blocking characteristics is alleviated by reducing the peak intensity of the electric field at the drain–side of the gate. There are two methods to reduce the peak intensity of the electric field: one is to decease the probability of tunneling of electrons into device active area the other is to relieve the crowding of electric field at the drain-side edge of gate. Nickel has been used as a gate electrode of the AlGaN/GaN HEMTs to form the Schottky contact due to its relatively high work function (5.15 eV). In this work, nickel oxide (NiOx) was inserted as the interfacial layer between main gate (Ni) and AlGaN barrier layer for improve the reliability of the AlGaN/GaN HEMTs. NiOx film was formed through the thermal oxidation in furnace. Material property of NiOx film depended on the two main factors: oxidation temperature, density of the film controlled by deposition rate. Only the NiOx film oxidized proper temperature range from 400℃ to 500℃ gave a favorable effect on the device performance. The NiOx film with high atomic density exhibited resistive switching characteristics, which can be used for GaN based memory device. Experiments to verify the effect of NiOx on reverse blocking operation were carried out. At the high temperature reverse bias (HTRB) test, it was found that work function of the NiOx was maintained. Moreover, it played an important role to improve the stable blocking operation. The result of electroluminescence (EL) analysis was consistent with the results obtained from HTRB test. Leakage current of the AlGaN/GaN HEMTs with NiOX interfacial layer measured at 200℃ was lower than that of the conventional device by 3 orders of magnitude. The breakdown voltage of the proposed device was up to 1.5 kV (1480 V). In recent years, improvements of the overall device performance were achieved by adopting metal-insulator-semiconductor (MIS) or metal-oxide-semiconductor (MOS) structure. At the gate region, by insulating gate electrode by means of a dielectric layer, electron injection is suppressed effectively. In this work, improvement of the blocking capability and reliability of AlGaN/GaN MIS-HEMTs employing atomic-layer-deposited (ALD) Al2O3 material was confirmed by experimental results. Mechanism responsible for the leakage current of the proposed device was investigated. Measured Leakage current of the fabricated MIS-HEMT was reduced to the range from sub pA (fA) to few pA. At the HTRB test, MIS-HEMT exhibited proved its thermal stability. Although drain leakage current (IDSS) was increased in proportion to the operational temperature, the leakage current of the proposed device was still lower than that of conventional device by 2 orders of magnitude. Breakdown voltage of the proposed device was up to 2 kV.Contents Abstract i List of Tables vii List of Figures ix 1. Introduction 1 1.1 Status quo of GaN power device 1 1.2 Research Background 26 1.3 Organization 42 2. Review of AlGaN/GaN HEMTs 45 2.1 Principle of AlGaN/GaN HEMTs 45 2.2 Structure and Polarization 55 2.3 Device fabrication 61 2.3.1 Pre-treatment 61 2.3.2 Isolation 63 2.3.3 Ohmic and Schottky contacts 67 2.4 Substrate used to AlGaN/GaN HEMTs 75 2.5 Factors limiting the HEMT performance 81 2.5.1 Current collapse 81 2.5.2 Leakage current 84 2.5.3 Breakdown mechanism and Failure 93 2.5.4 Technologies for high breakdown 102 3. AlGaN/GaN HEMT Employing NiOX Interfacial Layer 115 3.1 Overview 115 3.2 AlGaN/GaN HEMTs on SiC Substrate 117 3.2.1 Advantage of SiC substrate 117 3.2.2 Properties of HEMTs on SiC substrate 119 3.3 Device fabrication 122 3.4 Properties of the nickel oxide film 125 3.4.1 Resistive switching property of the NiOX 127 3.5 Device performance 138 3.5.1 Forward characteristics 138 3.5.2 Reverse blocking characteristics 151 3.6 Summary 173 4. AlGaN/GaN MOS-HEMT with ALD Al2O3 gate dielectric 174 4.1 AlGaN/GaN HEMT on Si Substrate 174 4.2 Atomic-Layer-Deposited Al2O3 dielectric 178 4.3 Device fabrication 186 4.4 Device performance 192 4.4.1 Forward characteristics 192 4.4.2 Reverse blocking characteristics 229 4.5 Summary 264 5. Conclusion. 265 Bibliography 268 초 록 286 감사의 글 290Docto

Advanced AlGaN/GaN HEMT technology, design, fabrication and characterization

Nowadays, the microelectronics technology is based on the mature and very well established silicon (Si) technology. However, Si exhibits some important limitations regarding its voltage blocking capability, operation temperature and switching frequency. In this sense, Gallium Nitride (GaN)-based high electron mobility transistors (HEMTs) devices have the potential to make this change possible. The unique combination of the high-breakdown field, the high-channel electron mobility of the two dimensional electron gas (2DEG), and high-temperature of operation has attracted enormous interest from social, academia and industry and in this context this PhD dissertation has been made. This thesis has focused on improving the device performance through the advanced design, fabrication and characterization of AlGaN/GaN HEMTs, primarily grown on Si templates. The first milestone of this PhD dissertation has been the establishment of a know-how on GaN HEMT technology from several points of view: the device design, the device modeling, the process fabrication and the advanced characterization primarily using devices fabricated at Centre de Recherche sur l'Hétéro-Epitaxie (CRHEA-CNRS) (France) in the framework of a collaborative project. In this project, the main workhorse of this dissertation was the explorative analysis performed on the AlGaN/GaN HEMTs by innovative electrical and physical characterization methods. A relevant objective of this thesis was also to merge the nanotechnology approach with the conventional characterization techniques at the device scale to understand the device performance. A number of physical characterization techniques have been imaginatively used during this PhD determine the main physical parameters of our devices such as the morphology, the composition, the threading dislocations density, the nanoscale conductive pattern and others. The conductive atomic force microscopy (CAFM) tool have been widely described and used to understand the conduction mechanisms through the AlGaN/GaN Ohmic contact by performing simultaneously topography and electrical conductivity measurements. As it occurs with the most of the electronic switches, the gate stack is maybe the critical part of the device in terms of performance and longtime reliability. For this reason, how the AlGaN/GaN HEMT gate contact affects the overall HEMT behaviour by means of advanced characterization and modeling has been intensively investigated. It is worth mentioning that the high-temperature characterization is also a cornerstone of this PhD. It has been reported the elevated temperature impact on the forward and the reverse leakage currents for analogous Schottky gate HEMTs grown on different substrates: Si, sapphire and free-standing GaN (FS-GaN). The HEMT' forward-current temperature coefficients (T^a) as well as the thermal activation energies have been determined in the range of 25-300 ºC. Besides, the impact of the elevated temperature on the Ohmic and gate contacts has also been investigated. The main results of the gold-free AlGaN/GaN HEMTs high-voltage devices fabricated with a 4 inch Si CMOS compatible technology at the clean room of the CNM in the framework of the industrial contract with ON semiconductor were presented. We have shown that the fabricated devices are in the state-of-the-art (gold-free Ohmic and Schottky contacts) taking into account their power device figure-of-merit ((VB^2)/Ron) of 4.05×10^8 W/cm^2. Basically, two different families of AlGaN/GaN-on-Si MIS-HEMTs devices were fabricated on commercial 4 inch wafers: (i) using a thin ALD HfO2 (deposited on the CNM clean room) and (ii) thin in-situ grown Si3N4, as a gate insulator (grown by the vendor). The scientific impact of this PhD in terms of science indicators is of 17 journal papers (8 as first author) and 10 contributions at international conferences

AlGaN/GaN based enhancement mode MOSHEMTs

This thesis describes a new gallium nitride (GaN) based transistor technology for electronic switching applications. Conventional GaN based transistors are of the high electron mobility transistor (HEMT) type and are depletion mode devices. These are not suitable for switching applications since an extra DC supply is required to bias the device in the cut-off (off-state) region and the devices are not fail-safe, i.e. incase of malfunction a short-circuit can exist between the main DC supply and ground. Enhancement mode (E-Mode) or normally-off devices can overcome these limitations and if realized in the GaN material system would benefit from the good material properties that support large breakdown voltages and low On-resistances. Fabrication of high performace E-mode GaN devices with low On-resistance and high breakdown voltage still remains a big challenge to date. In this thesis a new method for realizing enhancement mode aluminium gallium nitride - gallium nitride (AlGaN/GaN) devices using a localized gate-foot oxidation has been described. Thermal oxidation of the AlGaN barrier layer converts the top surface/part of this layer into aluminium oxide (Al2 O3 ) and gallium oxide (Ga2O3 ), which serve as a good gate dielectric and improve the gate leakage current by several orders of magnitude compared to a Schottky gate. The oxidation process leaves a thinner AlGaN barrier which can result in normally o§ operation. Without special precaution, however, the oxidation of the AlGaN barrier is not uniform from the top but occurs at higher rates at the defect/dislocation sites. This makes it impossible to control the barrier thickness and so rendering the barrier useless. To avoid the problem of non-uniform oxidation, a thin layer of aluminum is first deposited on the barrier layer and oxidized to form aluminium oxide on top. This additional oxide layer seems to ensure uniform oxidation of the AlGaN barrier layer underneath on subsequent further oxidation. Results of the fabricated 2 um x 100 um AlGaN/GaN MOS-HEMTs with a partially oxidized barrier layer showed a threshold voltage of -0.5 V (compared to -3 V for a Schottky devive fabricated on the same epilayer structure) and a maximum drain current of 800mA/mm at high gate bias of 5 V with very little current compression. The peak extrinsic transconductance of the device is 160 mS/mm at a drain-source voltage of 10 V with a very low specific On-resistance of 9:8 ohm.mm2 and an off-state breakdown voltage higher than 42 V. Capacitance-Voltage (C-V) measurements of Al2O3 /AlGaN /GaN circular test metal-oxide-semiconductor structures were observed and measured. They exhibit no hysteresis, indicating the good quality of the thermally grown aluminium oxide for realizing AlGaN/GaN based E-Mode devices for high frequency and high power applications

A review of technologies and design techniques of millimeter-wave power amplifiers

his article reviews the state-of-the-art millimeter-wave (mm-wave) power amplifiers (PAs), focusing on broadband design techniques. An overview of the main solid-state technologies is provided, including Si, gallium arsenide (GaAs), GaN, and other III-V materials, and both field-effect and bipolar transistors. The most popular broadband design techniques are introduced, before critically comparing through the most relevant design examples found in the scientific literature. Given the wide breadth of applications that are foreseen to exploit the mm-wave spectrum, this contribution will represent a valuable guide for designers who need a single reference before adventuring in the challenging task of the mm-wave PA design

Design, Modeling and Analysis of Non-classical Field Effect Transistors

Transistor scaling following per Moore\u27s Law slows down its pace when entering into nanometer regime where short channel effects (SCEs), including threshold voltage fluctuation, increased leakage current and mobility degradation, become pronounced in the traditional planar silicon MOSFET. In addition, as the demand of diversified functionalities rises, conventional silicon technologies cannot satisfy all non-digital applications requirements because of restrictions that stem from the fundamental material properties. Therefore, novel device materials and structures are desirable to fuel further evolution of semiconductor technologies. In this dissertation, I have proposed innovative device structures and addressed design considerations of those non-classical field effect transistors for digital, analog/RF and power applications with projected benefits. Considering device process difficulties and the dramatic fabrication cost, application-oriented device design and optimization are performed through device physics analysis and TCAD modeling methodology to develop design guidelines utilizing transistor\u27s improved characteristics toward application-specific circuit performance enhancement. Results support proposed device design methodologies that will allow development of novel transistors capable of overcoming limitation of planar nanoscale MOSFETs. In this work, both silicon and III-V compound devices are designed, optimized and characterized for digital and non-digital applications through calibrated 2-D and 3-D TCAD simulation. For digital functionalities, silicon and InGaAs MOSFETs have been investigated. Optimized 3-D silicon-on-insulator (SOI) and body-on-insulator (BOI) FinFETs are simulated to demonstrate their impact on the performance of volatile memory SRAM module with consideration of self-heating effects. Comprehensive simulation results suggest that the current drivability degradation due to increased device temperature is modest for both devices and corresponding digital circuits. However, SOI FinFET is recommended for the design of low voltage operation digital modules because of its faster AC response and better SCEs management than the BOI structure. The FinFET concept is also applied to the non-volatile memory cell at 22 nm technology node for low voltage operation with suppressed SCEs. In addition to the silicon technology, our TCAD estimation based on upper projections show that the InGaAs FinFET, with superior mobility and improved interface conditions, achieve tremendous drive current boost and aggressively suppressed SCEs and thereby a strong contender for low-power high-performance applications over the silicon counterpart. For non-digital functionalities, multi-fin FETs and GaN HEMT have been studied. Mixed-mode simulations along with developed optimization guidelines establish the realistic application potential of underlap design of silicon multi-Fin FETs for analog/RF operation. The device with underlap design shows compromised current drivability but improve analog intrinsic gain and high frequency performance. To investigate the potential of the novel N-polar GaN material, for the first time, I have provided calibrated TCAD modeling of E-mode N-polar GaN single-channel HEMT. In this work, I have also proposed a novel E-mode dual-channel hybrid MIS-HEMT showing greatly enhanced current carrying capability. The impact of GaN layer scaling has been investigated through extensive TCAD simulations and demonstrated techniques for device optimization