Plataforma para projeto de sistemas de rádio definidos por software

Mestrado em Engenharia Electrónica e TelecomunicaçõesEste trabalho tem como objetivos o projeto e a realização de uma plataforma para desenvolvimento de sistemas baseados em tecnologia Software Defined Radio (SDR). Num sistema SDR todas as tarefas de um rádio (ou pelo menos banda base e eventualmente Frequência Intermédia), anteriormente efetuadas por hardware especifico num contexto analógico, são efetuadas no domínio digital por software ou hardware reconfigurável. Esta característica confere a este tipo de rádio uma maior simplicidade, em termos de hardware bem como maior flexibilidade, pois o mesmo dispositivo pode executar diferentes funções apenas alterando o seu firmware/software. Existem diferentes abordagens relativas ao uso desta tecnologia, quer ao nível da arquitetura usada (varia consoante a frequência onde ocorre a digitalização do sinal), quer relativas á topologia de utilização (controlada por hardware reconfigurável, rotinas de software ou ambos). A motivação deste trabalho resulta na necessidade de concepção de uma plataforma para fins académicos baseada num hardware reprogramável, Field Programmable Gate Array (FPGA), de baixo custo, flexível, com interfaces de comunicação digitais e analógicas e que faculte a possibilidade de ser usada em diferentes topologias de utilização. Efetuada a especificação e o estudo necessário ao projeto bem como a escolha apropriada de componentes, conseguiu-se uma plataforma baseada num módulo FPGA contendo um dispositivo Xilinx, da família Spartan-6, bem como outro hardware relevante. A comunicação com outros dispositivos é assegurada por interfaces USB e gigabit Ethernet. A plataforma concebida está também equipada com interfaces analógicas (conversores AD/DA) bem como algumas interfaces de integração com o utilizador consistindo em switches e LEDs. Em suma foi projetada e desenhada uma plataforma aberta e flexível, que pode ser usada com todas as ferramentas de desenvolvimento, programação e depuração, com fácil acesso a todos os sinais relevantes potenciando a sua utilização para efeitos de ensino e investigação em SDR.The main objective of this dissertation relies on projecting and designing a platform suitable for Software De ned Radio (SDR) system development. On an SDR system all, or at least base band and maybe Intermediate Frequency (IF) radio functions, before handled by analog speci c hardware, are now performed on the digital domain by software or an recon gurable hardware device. This feature provides to this type of radios a major simplicity regarding hardware as well as another exibility level since, through a rmware/software upgrade, the same equipment can perform di erent functions. There are some approaches related to the used of this technology, either regarding architecture implementation (they di er in which frequency the digitalization occurs) or utilization topologies (an SDR device can be controlled by a recon gurable hardware, software routines or both). This project's motivation results from the need of designing a exible, low-cost platform, to be used on academic purposes, in which the central component would be a recon gurable hardware, a Field Programmable Gate Array (FPGA). It must provide both analog and digital interfaces so that can be used on various utilization scenarios. Accomplished all the necessary study, design and hardware selection the result is a platform based on an FPGA module, containing an Xilinx device from the Spartan-6 family as well as other relevant hardware. The interaction with other devices is ensured by both gigabit Ethernet and 2.0 Universal Serial Bus (USB) connections. The platform also features analog interfaces (AD/DA converters) as well as some digital end-user interfaces performed by switches and Light Emiter Diodes (LED)s. Concluding, it was built an open and exible platform in which can be use with all provided development, programming and debugging tools and all the relevant signals have easy access enhancing its use for teaching and researching on SDR technology

Design and Implementation of HD Wireless Video Transmission System Based on Millimeter Wave

With the improvement of optical fiber communication network construction and the improvement of camera technology, the video that the terminal can receive becomes clearer, with resolution up to 4K. Although optical fiber communication has high bandwidth and fast transmission speed, it is not the best solution for indoor short-distance video transmission in terms of cost, laying difficulty and speed. In this context, this thesis proposes to design and implement a multi-channel wireless HD video transmission system with high transmission performance by using the 60GHz millimeter wave technology, aiming to improve the bandwidth from optical nodes to wireless terminals and improve the quality of video transmission. This thesis mainly covers the following parts: (1) This thesis implements wireless video transmission algorithm, which is divided into wireless transmission algorithm and video transmission algorithm, such as 64QAM modulation and demodulation algorithm, H.264 video algorithm and YUV420P algorithm. (2) This thesis designs the hardware of wireless HD video transmission system, including network processing unit (NPU) and millimeter wave module. Millimeter wave module uses RWM6050 baseband chip and TRX-BF01 rf chip. This thesis will design the corresponding hardware circuit based on the above chip, such as 10Gb/s network port, PCIE. (3) This thesis realizes the software design of wireless HD video transmission system, selects FFmpeg and Nginx to build the sending platform of video transmission system on NPU, and realizes video multiplex transmission with Docker. On the receiving platform of video transmission, FFmpeg and Qt are selected to realize video decoding, and OpenGL is combined to realize video playback. (4) Finally, the thesis completed the wireless HD video transmission system test, including pressure test, Web test and application scenario test. It has been verified that its HD video wireless transmission system can transmit HD VR video with three-channel bit rate of 1.2GB /s, and its rate can reach up to 3.7GB /s, which meets the research goal

WDM/TDM PON bidirectional networks single-fiber/wavelength RSOA-based ONUs layer 1/2 optimization

This Thesis proposes the design and the optimization of a hybrid WDM/TDM PON at the L1 (PHY) and L2 (MAC) layers, in terms of minimum deployment cost and enhanced performance for Greenfield NGPON. The particular case of RSOA-based ONUs and ODN using a single-fibre/single-wavelength is deeply analysed. In this WDM/TDM PON relevant parameters are optimized. Special attention has been given at the main noise impairment in this type of networks: the Rayleigh Backscattering effect, which cannot be prevented. To understand its behaviour and mitigate its effects, a novel mathematical model for the Rayleigh Backscattering in burst mode transmission is presented for the first time, and it has been used to optimize the WDM/TDM RSOA based PON. Also, a cost-effective, simple design SCM WDM/TDM PON with rSOA-based ONU, was optimized and implemented. This prototype was successfully tested showing high performance, robustness, versatility and reliability. So, the system is able to give coverage up to 1280 users at 2.5 Gb/s / 1.25 Gb/s downstream/upstream, over 20 Km, and being compatible with the GPON ITU-T recommendation. This precedent has enabled the SARDANA network to extend the design, architecture and capabilities of a WDM/TDM PON for a long reach metro-access network (100 km). A proposal for an agile Transmission Convergence sub-layer is presented as another relevant contribution of this work. It is based on the optimization of the standards GPON and XG-PON (for compatibility), but applied to a long reach metro-access TDM/WDM PON rSOA-based network with higher client count. Finally, a proposal of physical implementation for the SARDANA layer 2 and possible configurations for SARDANA internetworking, with the metro network and core transport network, are presented

The design and implementation of a carrier card for the Karoo Array Telescope

Does not include abstract.Includes bibliographical references (leaf 56).The Karoo Array Telescope [KAT] is a South African project that is attempting to build a worldclass radio telescope in the Northern Cape. The first prototype phase of the project was called the eXperimental Development Model or XDM. This MSc project involves the development of a carrier card that was planned to be used for XDM. The card, called the XDM Carrier Card, or XCC, was designed to be used as part of a modular Digital Signal Processing [DSP] architecture

Experimental Evaluation and Comparison of Time-Multiplexed Multi-FPGA Routing Architectures

Emulating large complex designs require multi-FPGA systems (MFS). However, inter-FPGA communication is confronted by the challenge of lack of interconnect capacity due to limited number of FPGA input/output (I/O) pins. Serializing parallel signals onto a single trace effectively addresses the limited I/O pin obstacle. Besides the multiplexing scheme and multiplexing ratio (number of inter-FPGA signals per trace), the choice of the MFS routing architecture also affect the critical path latency. The routing architecture of an MFS is the interconnection pattern of FPGAs, fixed wires and/or programmable interconnect chips. Performance of existing MFS routing architectures is also limited by off-chip interface selection. In this dissertation we proposed novel 2D and 3D latency-optimized time-multiplexed MFS routing architectures. We used rigorous experimental approach and real sequential benchmark circuits to evaluate and compare the proposed and existing MFS routing architectures. This research provides a new insight into the encouraging effects of using off-chip optical interface and three dimensional MFS routing architectures. The vertical stacking results in shorter off-chip links improving the overall system frequency with the additional advantage of smaller footprint area. The proposed 3D architectures employed serialized interconnect between intra-plane and inter-plane FPGAs to address the pin limitation problem. Additionally, all off-chip links are replaced by optical fibers that exhibited latency improvement and resulted in faster MFS. Results indicated that exploiting third dimension provided latency and area improvements as compared to 2D MFS. We also proposed latency-optimized planar 2D MFS architectures in which electrical interconnections are replaced by optical interface in same spatial distribution. Performance evaluation and comparison showed that the proposed architectures have reduced critical path delay and system frequency improvement as compared to conventional MFS. We also experimentally evaluated and compared the system performance of three inter-FPGA communication schemes i.e. Logic Multiplexing, SERDES and MGT in conjunction with two routing architectures i.e. Completely Connected Graph (CCG) and TORUS. Experimental results showed that SERDES attained maximum frequency than the other two schemes. However, for very high multiplexing ratios, the performance of SERDES & MGT became comparable

FirstLight: Pluggable Optical Interconnect Technologies for Polymeric Electro-Optical Printed Circuit Boards in Data Centers

The protocol data rate governing data storage devices will increase to over 12 Gb/s by 2013 thereby imposing unmanageable cost and performance burdens on future digital data storage systems. The resulting performance bottleneck can be substantially reduced by conveying high-speed data optically instead of electronically. A novel active pluggable 82.5 Gb/s aggregate bit rate optical connector technology, the design and fabrication of a compact electro-optical printed circuit board to meet exacting specifications, and a method for low cost, high precision, passive optical assembly are presented. A demonstration platform was constructed to assess the viability of embedded electro-optical midplane technology in such systems including the first ever demonstration of a pluggable active optical waveguide printed circuit board connector. High-speed optical data transfer at 10.3125 Gb/s was demonstrated through a complex polymer waveguide interconnect layer embedded into a 262 mm × 240 mm × 4.3 mm electro-optical midplane. Bit error rates of less than 10-12 and optical losses as low as 6 dB were demonstrated through nine multimode polymer wave guides with an aggregate data bandwidth of 92.8125 Gb/s

Performance measurement and analysis of PC based cluster server using SET of Architecture and modeling a scalable High performance cluster

Not availabl

Medium Access Control Layer Implementation on Field Programmable Gate Array Board for Wireless Networks

Triple play services are playing an important role in modern telecommunications systems. Nowadays, more researchers are engaged in investigating the most efficient approaches to integrate these services at a reduced level of operation costs. Field Programmable Gate Array (FPGA) boards have been found as the most suitable platform to test new protocols as they offer high levels of flexibility and customization. This thesis focuses on implementing a framework for the Triple Play Time Division Multiple Access (TP-TDMA) protocol using the Xilinx FPGA Virtex-5 board. This flexible framework design offers network systems engineers a reconfigiirable platform for triple-play systems development. In this work, MicorBlaze is used to perform memory and connectivity tests aiming to ensure the establishment of the connectivity as well as board’s processor stability. Two different approaches are followed to achieve TP-TDMA implementa­tion: systematic and conceptual. In the systematic approach, a bottom-to-top design is chosen where four subsystems are built with various components. Each component is then tested individually to investigate its response. On the other hand, the concep­tual approach is designed with only two components, in which one of them is created with the help of Xilinx Integrated Software Environment (ISE) Core Generator. The system is integrated and then tested to check its overall response. In summary, the work of this thesis is divided into three sections. The first section presents a testing method for Virtex-5 board using MicroBlaze soft processor. The following two sections concentrate on implementing the TP-TDMA protocol on the board by using two design approaches: one based on designing each component from scratch, while the other one focuses more on the system’s broader picture

From FPGA to ASIC: A RISC-V processor experience

This work document a correct design flow using these tools in the Lagarto RISC- V Processor and the RTL design considerations that must be taken into account, to move from a design for FPGA to design for ASIC

RHINO: reconfigurable hardware interface for computation and radio

Field-programmable gate arrays, or FPGAs, provide an attractive computing platform for software-defined radio applications. Their reconfigurable nature allows many digital signal processing (DSP) algorithms to be highly parallelised within the FPGA fabric, while their customisable I/O interfaces allow simple interfacing to analogue-to-digital converters (ADCs) and digital-to-analogue converters (DACs). However, FPGA boards that deliver sufficient performance to be useful in real-world applications are generally expensive. Rhino is an FPGA-based hardware processing platform that primarily supports software-defined radio applications. The final cost estimate for a complete Rhino system is under $1700, cheaper than similar FPGA boards that deliver much lower performance