Triple play services are playing an important role in modern telecommunications systems. Nowadays, more researchers are engaged in investigating the most efficient approaches to integrate these services at a reduced level of operation costs. Field Programmable Gate Array (FPGA) boards have been found as the most suitable platform to test new protocols as they offer high levels of flexibility and customization. This thesis focuses on implementing a framework for the Triple Play Time Division Multiple Access (TP-TDMA) protocol using the Xilinx FPGA Virtex-5 board. This flexible framework design offers network systems engineers a reconfigiirable platform for triple-play systems development.
In this work, MicorBlaze is used to perform memory and connectivity tests aiming to ensure the establishment of the connectivity as well as board’s processor stability. Two different approaches are followed to achieve TP-TDMA implementation: systematic and conceptual. In the systematic approach, a bottom-to-top design is chosen where four subsystems are built with various components. Each component is then tested individually to investigate its response. On the other hand, the conceptual approach is designed with only two components, in which one of them is created with the help of Xilinx Integrated Software Environment (ISE) Core Generator. The system is integrated and then tested to check its overall response.
In summary, the work of this thesis is divided into three sections. The first section presents a testing method for Virtex-5 board using MicroBlaze soft processor. The following two sections concentrate on implementing the TP-TDMA protocol on the board by using two design approaches: one based on designing each component from scratch, while the other one focuses more on the system’s broader picture
