Design And Implementation Of A Digital Controller With Dsp For Half-br

DC-DC power converters play an important role in powering telecom and computing systems. With the speed improvement and cost reduction of digital control, digital controller is becoming a trend for DC-DC converters in addition to existed digital monitoring and management technology. In this thesis, digital control is investigated for DC-DC converters applications. To deeply understand the whole control systems, DC-DC converter models are investigated based on averaged state-space modeling. Considering half-bridge isolated DC-DC converter with a current doublers rectifier has advantages over other topologies especially in the application of low-voltage and high-current DC-DC converters, the thesis take it as an example for digital control modeling and implementation. In Chapter 2, unified steady-state DC models and small-signal models are developed for both symmetric and asymmetric controlled half-bridge DC-DC converters. Based on the models, digital controller design is implemented. In Chapter 3, digital modeling platforms are established based on Matlab, Digital PID design and corresponding simulation results are provided. Also some critical issues and practical requirements are discussed. In Chapter 4, a DSP-based digital controller is implemented with the TI\u27s DSP chip TMS320F2812. Related implementation methods and technologies are discussed. Finally the experimental results of a DSP-based close-loop of HB converter are provided and analyzed in Chapter 5, and thesis conclusions are given in Chapter 6

Digital Pulse Width Modulator Techniques For Dc - Dc Converters

Recent research activities focused on improving the steady-state as well as the dynamic behavior of DC-DC converters for proper system performance, by proposing different design methods and control approaches with growing tendency to using digital implementation over analog practices. Because of the rapid advancement in semiconductors and microprocessor industry, digital control grew in popularity among PWM converters and is taking over analog techniques due to availability of fast speed microprocessors, flexibility and immunity to noise and environmental variations. Furthermore, increased interest in Field Programmable Gate Arrays (FPGA) makes it a convenient design platform for digitally controlled converters. The objective of this research is to propose new digital control schemes, aiming to improve the steady-state and transient responses of a high switching frequency FPGA-based digitally controlled DC-DC converters. The target is to achieve enhanced performance in terms of tight regulation with minimum power consumption and high efficiency at steady-state, as well as shorter settling time with optimal over- and undershoots during transients. The main task is to develop new and innovative digital PWM techniques in order to achieve: 1. Tight regulation at steady-state: by proposing high resolution DPWM architecture, based on Digital Clock Management (DCM) resources available on FPGA boards. The proposed architecture Window-Masked Segmented Digital Clock Manager-FPGA based Digital Pulse Width Modulator Technique, is designed to achieve high resolution operating at high switching frequencies with minimum power consumption. 2. Enhanced dynamic response: by applying a shift to the basic saw-tooth DPWM signal, in order to benefit from the best linearity and simplest architecture offered by the conventional counter-comparator DPWM. This proposed control scheme will help the compensator reach the steady-state value faster. Dynamically Shifted Ramp Digital Control Technique for Improved Transient Response in DC-DC Converters, is projected to enhance the transient response by dynamically controlling the ramp signal of the DPWM unit

Digital Pulse Width Modulation Generation Using 8051 for DC DC Buck Converter

The research on digital control of DC-DC converters is mainly focused on two areas. One is the methods to generate digital PWM (DPWM) signals to meet the output voltage requirement precisely. Various techniques have been developed to meet the requirement of output voltage and at the same time it is also necessary to get more resolution to increase precision. The other is to develop new control methods that can utilize the advantages of the digital controller so as to improve the dynamic performance of the switching power converters. The objective of this thesis is to study current techniques of DPWM generation and to develop new techniques using 8051 for low cost implementation. In this thesis a new way is proposed for PWM generation, which uses the Timers and Interrupts of 8051. Motivation behind selecting 8051 microcontroller is its low cost and ease of programming, despite its disadvantages, like low clock frequency (33 MHz for 89C51RD2, which in internally divided by 12), no inbuilt ADC or DAC. Initially different techniques are validated in NI Multisim environment and also the proposed method is validated on the same platform for a dc-dc buck converter. This thesis also compares the designed new approach with the delay line method of DPWM generation with simulation result. The delay line method is also implemented in 8051 for comparison with the new designed method

Study and comparison of discontinuous modulation for modular multilevel converters in motor drive applications

Discontinuous modulation applied to modular multilevel converters is an effective method for reducing the capacitor voltage ripples. In this paper, the discontinuous modulation is adapted and used in a motor drive application. For proper operation of the converter, a new energy controller is presented, which is suitable for operation with nonsinusoidal reference signals. Experimental results comparing the discontinuous modulation with other techniques operating at low motor speeds are shown. The results demonstrate the effectiveness of the discontinuous modulation on reducing capacitor voltage ripples and power losses.Postprint (published version

Active current sharing control schemes for parallel connected AC/DC/AC converters

PhD ThesisThe parallel operation of voltage fed converters can be used in many applications, such as aircraft, aerospace, and wind turbines, to increase the current handling capability, system efficiency, flexibility, and reliability through providing redundancy. Also, the maintenance of low power parallel connected units is lower than one high power unit. Significant performance improvement can be attained with parallel converters employing interleaving techniques where small passive components can be used due to harmonic cancellation. In spite of the advantages offered by parallel connected converters, the circulating current problem is still a major concern. The term circulating current describes the uneven current sharing between the units. This circulating current leads to: current distortion, unbalanced operation, which possibly damages the converters, and a reduction in overall system performance. Therefore, current sharing control methods become necessary to limit the circulating current in a parallel connected converter system. The work in this thesis proposes four active current sharing control schemes for two equally rated, directly paralleled, AC/DC/AC converters. The first scheme is referred to as a “time sharing approach,” and it divides the operation time between the converters. Accordingly, in the scheme inter-module reactors become unnecessary, as these are normally employed at the output of each converter. However, this approach can only be used with a limited number of parallel connected units. To avoid this limitation, three other current sharing control schemes are proposed. Moreover, these three schemes can be adopted with any pulse width modulation (PWM) strategy and can be easily extended to three or more parallel connected units since they employ a modular architecture. The proposed current sharing control methods are employed in two applications: a current controller for three-phase RL load and an open loop V/f speed control for a three-phase induction motor. The performance of the proposed methods is verified in both transient and steady state conditions using numerical simulation and experimental testingMinistry of Higher Education and Scientific Research of Iraq

Adaptive Efficiency Optimization For Digitally Controlled Dc-dc Converters

The design optimization of DC-DC converters requires the optimum selection of several parameters to achieve improved efficiency and performance. Some of these parameters are load dependent, line dependent, components dependent, and/or temperature dependent. Designing such parameters for a specific load, input and output, components, and temperature may improve single design point efficiency but will not result in maximum efficiency at different conditions, and will not guarantee improvement at that design point because of the components, temperature, and operating point variations. The ability of digital controllers to perform sophisticated algorithms makes it easy to apply adaptive control, where system parameters can be adaptively adjusted in response to system behavior in order to achieve better performance and stability. The use of adaptive control for power electronics is first applied with the Adaptive Frequency Optimization (AFO) method, which presents an auto-tuning adaptive digital controller with maximum efficiency point tracking to optimize DC-DC converter switching frequency. The AFO controller adjusts the DC-DC converter switching frequency while tracking the converter minimum input power point, under variable operating conditions, to find the optimum switching frequency that will result in minimum total loss and thus the maximum efficiency. Implementing variable switching frequencies in digital controllers introduces two main issues, namely, limit cycle oscillation and system instability. Dynamic Limit Cycle Algorithms (DLCA) is a dynamic technique tailored to improve system stability and to reduce limit cycle oscillation under variable switching frequency operation. The convergence speed and stability of AFO algorithm is further improved by presenting the analysis and design of a digital controller with adaptive auto-tuning algorithm that has a variable step size to track and detect the optimum switching frequency for a DC-DC converter. The Variable-Step-Size (VSS) algorithm is theoretically analyzed and developed based on buck DC-DC converter loss model and directed towered improving the convergence speed and accuracy of AFO adaptive loop by adjusting the converter switching frequency with variable step size. Finally, the efficiency of DC-DC converters is a function of several variables. Optimizing single variable alone may not result in maximum or global efficiency point. The issue of adjusting more than one variable at the same time is addressed by the Multivariable Adaptive digital Controller (MVAC). The MVAC is an adaptive method that continuously adjusts the DC-DC converter switching frequency and dead-time at the same time, while tracking the converter minimum input power, to find the maximum global efficiency point under variable conditions. In this research work, all adaptive methods were discussed, theoretically analyzed and its digital control algorithm along with experimental implementations were presented

Synthesizable delay line architectures for digitally controlled voltage regulators

Voltage regulators used in the integrated circuit (IC) industry require precise voltage regulation. In digitally controlled switching converters, this precise voltage regulation is achieved by high resolution digital pulse width modulators (DPWM). Digital delay lines can be used to generate the pulse width modulation (PWM) signal. Conventional delay lines are designed in a full custom design methodology which is extremely slow and expensive compared to register-transfer level (RTL) based designs; also RTL based designs are technology independent so the same design can be used with new technologies. The purpose of this work is to introduce a new architecture for the fully synthesizable digital delay line used in digitally controlled voltage regulators. A comparison between the proposed scheme and the conventional delay line is done post synthesis on the key delay line specifications like linearity, area, complexity, and compensation for process, voltage, and temperature (PVT) variations for multiple clock frequencies. Both schemes are designed using a hardware description language (HDL) and synthesized using Intel 32nm technology. The comparison showed that the proposed architecture has better linearity, area, and also it has a fast calibration time with respect to conventional delay lines. The delay lines are designed in parameterized way in order to make the design suitable for multiple frequencies