Motion estimation and CABAC VLSI co-processors for real-time high-quality H.264/AVC video coding

Real-time and high-quality video coding is gaining a wide interest in the research and industrial community for different applications. H.264/AVC, a recent standard for high performance video coding, can be successfully exploited in several scenarios including digital video broadcasting, high-definition TV and DVD-based systems, which require to sustain up to tens of Mbits/s. To that purpose this paper proposes optimized architectures for H.264/AVC most critical tasks, Motion estimation and context adaptive binary arithmetic coding. Post synthesis results on sub-micron CMOS standard-cells technologies show that the proposed architectures can actually process in real-time 720 × 480 video sequences at 30 frames/s and grant more than 50 Mbits/s. The achieved circuit complexity and power consumption budgets are suitable for their integration in complex VLSI multimedia systems based either on AHB bus centric on-chip communication system or on novel Network-on-Chip (NoC) infrastructures for MPSoC (Multi-Processor System on Chip

Hardware study on the H.264/AVC video stream parser

The video standard H.264/AVC is the latest standard jointly developed in 2003 by the ITUT Video Coding Experts Group (VCEG) and the ISO/IEC Moving Picture Experts Group (MPEG). It is an improvement over previous standards, such as MPEG-1 and MPEG-2, as it aims to be efficient for a wide range of applications and resolutions, including high definition broadcast television and video for mobile devices. Due to the standardization of the formatted bit stream and video decoder many more applications can take advantage of the abstraction this standard provides by implementing a desired video encoder and simply adhering to the bit stream constraints. The increase in application flexibility and variable resolution support results in the need for more sophisticated decoder implementations and hardware designs become a necessity. It is desirable to consider architectures that focus on the first stage of the video decoding process, where all data and parameter information are recovered, to understand how influential the initial step is to the decoding process and how influential various targeting platforms can be. The focus of this thesis is to study the differences between targeting an original video stream parser architecture for a 65nm ASIC (Application Specific Integrated Circuit), as well as an FPGA (Field Programmable Gate Array). Previous works have concentrated on designing parts of the parser and using numerous platforms; however, the comparison of a single architecture targeting different platforms could lead to further insight into the video stream parser. Overall, the ASIC implementations showed higher performance and lower area than the FPGA, with a 60% increase in performance and 6x decrease in area. The results also show the presented design to be a low power architecture, when compared to other research

Low power context adaptive variable length encoder in H.264

The adoption of digital TV, DVD video and Internet streaming led to the development of Video compression. H.264/AVC is the industry standard delivering highly efficient and reliable video compression. In this Video compression standard, H.264/AVC one of the technical developments adopted is the Context adaptive entropy coding schemes. This thesis developed a complete VHDL behavioral model of a variable length encoder. A synthesizable hardware description is then developed for components of the variable length encoder using Synopsys tools. Many implementations were focused on density and speed to reduce the hardware cost and improve quality but with higher power consumption. Low power consumption of an IC leads to lower heat dissipation and thereby reduces the need for bigger heat sinking devices. Reducing the need for heat sinking devices can provide lot of advantages to the manufacturers in terms of cost and size of the end product. Focus towards smaller area with higher power consumption may not be appropriate for some end products that need thinner mechanical enclosures because even if the design has smaller area it needs a bigger heat sink thereby making the enclosures bigger. This thesis therefore aimed at low power consumption without compromising much on the area. The designed architecture enables real-time processing for QCIF and CIF frames with 60-fps using 100MHz clock. The resultant hardware power is 1.4mW at 100MHz using 65nm technology. The total logic gate count is 32K gates

CABAC accelerator architectures for video compression in future multimedida : a survey

The demands for high quality, real-time performance and multi-format video support in consumer multimedia products are ever increasing. In particular, the future multimedia systems require efficient video coding algorithms and corresponding adaptive high-performance computational platforms. The H.264/AVC video coding algorithms provide high enough compression efficiency to be utilized in these systems, and multimedia processors are able to provide the required adaptability, but the algorithms complexity demands for more efficient computing platforms. Heterogeneous (re-)configurable systems composed of multimedia processors and hardware accelerators constitute the main part of such platforms. In this paper, we survey the hardware accelerator architectures for Context-based Adaptive Binary Arithmetic Coding (CABAC) of Main and High profiles of H.264/AVC. The purpose of the survey is to deliver a critical insight in the proposed solutions, and this way facilitate further research on accelerator architectures, architecture development methods and supporting EDA tools. The architectures are analyzed, classified and compared based on the core hardware acceleration concepts, algorithmic characteristics, video resolution support and performance parameters, and some promising design directions are discussed. The comparative analysis shows that the parallel pipeline accelerator architecture seems to be the most promising

Efficient H.264 intra Frame CODEC with Best prediction matrix mode algorithm

The continuous growth of smart communities and everincreasingdemand of sending or storing videos, have led toconsumption of huge amount of data. The video compressiontechniques are solving this emerging challenge. However, H.264standard can be considered most notable, and it has proven to meetproblematic requirements. The authors present (BPMM) as a novelefficient Intra prediction scheme. We can say that the creation of ourproposed technique was in a phased manner; it\u27s emerged as aproposal and achieved impressive results in the performanceparameters as compression ratios, bit rates, and PSNR. Then in thesecond stage, we solved the challenges of overcoming the obstacle ofencoding bits overhead. In this research, we try to address the finalphase of the (BPMM) codec and to introduce our approach in a globalmanner through realization of decoding mechanism. For evaluation ofour scheme, we utilized VHDL as a platform. Final results haveproven our success to pass bottleneck of this phase, since the decodedvideos have the same PSNR that our encoder tells us, whilepreserving steady compression ratio treating the overhead. We aspireour BPMM algorithm will be adopted as reference design of H.264 inthe ITU

Efficient H.264 intra Frame CODEC with Best prediction matrix mode algorithm

The continuous growth of smart communities and everincreasingdemand of sending or storing videos, have led toconsumption of huge amount of data. The video compressiontechniques are solving this emerging challenge. However, H.264standard can be considered most notable, and it has proven to meetproblematic requirements. The authors present (BPMM) as a novelefficient Intra prediction scheme. We can say that the creation of ourproposed technique was in a phased manner; it's emerged as aproposal and achieved impressive results in the performanceparameters as compression ratios, bit rates, and PSNR. Then in thesecond stage, we solved the challenges of overcoming the obstacle ofencoding bits overhead. In this research, we try to address the finalphase of the (BPMM) codec and to introduce our approach in a globalmanner through realization of decoding mechanism. For evaluation ofour scheme, we utilized VHDL as a platform. Final results haveproven our success to pass bottleneck of this phase, since the decodedvideos have the same PSNR that our encoder tells us, whilepreserving steady compression ratio treating the overhead. We aspireour BPMM algorithm will be adopted as reference design of H.264 inthe ITU

Mengenal pasti tahap pengetahuan pelajar tahun akhir Ijazah Sarjana Muda Kejuruteraan di KUiTTHO dalam bidang keusahawanan dari aspek pengurusan modal

Malaysia ialah sebuah negara membangun di dunia. Dalam proses pembangunan ini, hasrat negara untuk melahirkan bakal usahawan beijaya tidak boleh dipandang ringan. Oleh itu, pengetahuan dalam bidang keusahawanan perlu diberi perhatian dengan sewajarnya; antara aspek utama dalam keusahawanan ialah modal. Pengurusan modal yang tidak cekap menjadi punca utama kegagalan usahawan. Menyedari hakikat ini, kajian berkaitan Pengurusan Modal dijalankan ke atas 100 orang pelajar Tahun Akhir Kejuruteraan di KUiTTHO. Sampel ini dipilih kerana pelajar-pelajar ini akan menempuhi alam pekeijaan di mana mereka boleh memilih keusahawanan sebagai satu keijaya. Walau pun mereka bukanlah pelajar dari jurusan perniagaan, namun mereka mempunyai kemahiran dalam mereka cipta produk yang boleh dikomersialkan. Hasil dapatan kajian membuktikan bahawa pelajar-pelajar ini berminat dalam bidang keusahawanan namun masih kurang pengetahuan tentang pengurusan modal terutamanya dalam menentukan modal permulaan, pengurusan modal keija dan caracara menentukan pembiayaan kewangan menggunakan kaedah jualan harian. Oleh itu, satu garis panduan Pengurusan Modal dibina untuk memberi pendedahan kepada mereka

CAL Dataflow Components for an MPEG RVC AVC Baseline Encoder

In this paper, an efficient H.264/AVC baseline encoder, described in RVC-CAL actor language, is introduced. The main aim of the paper is twofold: a) to demonstrate the flexibility and ease that is provided by RVC-CAL, which allows for efficient implementation of the presented encoder, and b) to shed light on the advantages that can be brought into the RVC framework by including such encoding tools. The main modules of the designed encoder include: Inter Frame Prediction (Motion Estimation/Compensation), Intra Frame Prediction, and Entropy Coding. Descriptions of the designed modules, accompanied with RVC-CAL design issues are provided. A comparison between different development approaches is also provided. The obtained results show that specifying complex video codecs (e.g. H.264/AVC encoder) using RVC-CAL followed by automatic translation into HDL, which is achievable by the tools that support the standard, results in more efficient HW implementation compared to the traditional HW design flow. A discussion that explains the reasons behind such results concludes the pape

SIMD based multicore processor for image and video processing

制度:新 ; 報告番号:甲3602号 ; 学位の種類:博士(工学) ; 授与年月日:2012/3/15 ; 早大学位記番号:新595