73 research outputs found
Solid State Circuits Technologies
The evolution of solid-state circuit technology has a long history within a relatively short period of time. This technology has lead to the modern information society that connects us and tools, a large market, and many types of products and applications. The solid-state circuit technology continuously evolves via breakthroughs and improvements every year. This book is devoted to review and present novel approaches for some of the main issues involved in this exciting and vigorous technology. The book is composed of 22 chapters, written by authors coming from 30 different institutions located in 12 different countries throughout the Americas, Asia and Europe. Thus, reflecting the wide international contribution to the book. The broad range of subjects presented in the book offers a general overview of the main issues in modern solid-state circuit technology. Furthermore, the book offers an in depth analysis on specific subjects for specialists. We believe the book is of great scientific and educational value for many readers. I am profoundly indebted to the support provided by all of those involved in the work. First and foremost I would like to acknowledge and thank the authors who worked hard and generously agreed to share their results and knowledge. Second I would like to express my gratitude to the Intech team that invited me to edit the book and give me their full support and a fruitful experience while working together to combine this book
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Automatic synthesis of analog layout : a survey
A review of recent research in the automatic synthesis of physical geometry for analog integrated circuits is presented. On introduction, an explanation of the difficulties involved in analog layout as opposed to digital layout is covered. Review of the literature then follows. Emphasis is placed on the exposition of general methods for addressing problems specific to analog layout, with the details of specific systems only being given when they surve to illustrate these methods well. The conclusion discusses problems remaining and offers a prediction as to how technology will evolve to solve them. It is argued that although progress has been and will continue to be made in the automation of analog IC layout, due to fundamental differences in the nature of analog IC design as opposed to digital design, it should not be expected that the level of automation of the former will reach that of the latter any time soon
์ ์ ์๊ณ ๋ฆฌ์ฆ ๋ฐ ๊ฐํํ์ต์ ์ฌ์ฉํ ๊ณ ์ ํ๋ก ์ค๊ณ ์๋ํ ํ๋ ์์ํฌ
ํ์๋
ผ๋ฌธ(์์ฌ) -- ์์ธ๋ํ๊ต๋ํ์ : ์ตํฉ๊ณผํ๊ธฐ์ ๋ํ์ ์ง๋ฅ์ ๋ณด์ตํฉํ๊ณผ, 2022.2. ์ ๋์.Although design automation is a key enabler of modern large-scale digital systems, automating the transistor-level circuit design process still remains a challenge. Some recent works suggest that deep learning algorithms could be adopted to find optimal transistor dimensions in relatively small circuitry such as analog amplifiers. However, those approaches are not capable of exploring different circuit structures to meet the given design constraints. In this work, we propose an automatic circuit design framework that can generate practical circuit structures from scratch as well as optimize the size of each transistor, considering performance and reliability. We employ the framework to design level shifter circuits, and the experimental results show that the framework produces novel level shifter circuit topologies and the automatically optimized designs achieve 2.8-5.3ร lower PDP than prior arts designed by human experts.์ค๊ณ ์๋ํ๋ ๋๊ท๋ชจ ๋์งํธ ์์คํ
์ ๊ฐ๋ฅํ๊ฒ ํ๋ ํต์ฌ ์์์ด์ง๋ง ํธ๋์ง์คํฐ ์์ค์์ ํ๋ก ์ค๊ณ ํ๋ก์ธ์ค๋ฅผ ์๋ํํ๋ ๊ฒ์ ์ฌ์ ํ ์ด๋ ค์ด ๊ณผ์ ๋ก ๋จ์ ์์ต๋๋ค. ์ต๊ทผ ์ฐ๊ตฌ์์๋ ์๋ ๋ก๊ทธ ์ฐํ์ ๊ฐ์ ๋น๊ต์ ์์ ํ๋ก์์ ์ต์ ์ ์ฑ๋ฅ์ ๋ณด์ด๋ ํธ๋์ง์คํฐ ํฌ๊ธฐ๋ฅผ ์ฐพ๊ธฐ ์ํด deep learning ์๊ณ ๋ฆฌ์ฆ์ ํ์ฉํ ์ ์๋ค๊ณ ๋งํฉ๋๋ค. ๊ทธ๋ฌ๋ ์ด๋ฌํ ์ ๊ทผ ๋ฐฉ์์ ์ฃผ์ด์ง ์ค๊ณ constraint๋ฅผ ์ถฉ์กฑํ๋ ๋ค๋ฅธ ํ๋ก ๊ตฌ์กฐ ํ์์ ์ ์ฉํ๊ธฐ ์ด๋ ต์ต๋๋ค. ๋ณธ ์ฐ๊ตฌ์์๋ ์ฑ๋ฅ๊ณผ ์ ๋ขฐ์ฑ์ ๊ณ ๋ คํ์ฌ ๊ฐ ํธ๋์ง์คํฐ์ ํฌ๊ธฐ๋ฅผ ์ต์ ํํ ๋ฟ๋ง ์๋๋ผ ์ฒ์๋ถํฐ ์ค์ฉ์ ์ธ ํ๋ก ๊ตฌ์กฐ๋ฅผ ์์ฑํ ์ ์๋ ์๋ ํ๋ก ์ค๊ณ framework๋ฅผ ์ ์ํฉ๋๋ค. ์ฐ๋ฆฌ๋ framework๋ฅผ ์ฌ์ฉํ์ฌ level shifter ํ๋ก๋ฅผ ์ค๊ณํ์ผ๋ฉฐ ์คํ ๊ฒฐ๊ณผ๋ ํ๋ ์์ํฌ๊ฐ ์๋ก์ด level shifter ํ๋ก ํ ํด๋ก์ง๋ฅผ ์์ฑํ๊ณ ์๋์ผ๋ก ์ต์ ํ๋ ์ค๊ณ๊ฐ ์ธ๊ฐ ์ ๋ฌธ๊ฐ๊ฐ ์ค๊ณํ ์ ํ ๊ธฐ์ ๋ณด๋ค 2.8-5.3๋ฐฐ ๋ ๋ฎ์ PDP๋ฅผ ๋ฌ์ฑํ๋ค๋ ๊ฒ์ ๋ณด์ฌ์ค๋๋ค.Abstract i
Contents ii
List of Tables iv
List of Figures v
List of Algorithms vi
1 Introduction 1
2 Related work 6
2.1 Genetic Algorithm 6
2.2 NeuroEvolution of Augmenting Topologies (NEAT) 7
2.3 Reinforcement Learning (RL) 10
2.4 DDPG, D4PG, and PPO 12
2.5 Level Shifter 14
3 Proposed circuit design framework 17
3.1 Topology Generator 17
3.2 Circuit Optimizer 25
4 Experiment Result 32
4.1 Level Shifter Design 32
4.2 Topology Generation 34
4.3 Circuit Optimization 36
4.4 Test Chip Fabrication 42
4.5 Applicability of Topology Generator 47
5 Conclusion 50
Abstract (In Korean) 57์
3D modeling and integration of current and future interconnect technologies
Title from PDF of title page viewed June 21, 2021Dissertation advisor: Masud H. ChowdhuryVitaIncludes bibliographical references (pages 133-138)Thesis (Ph.D.)--School of Computing and Engineering and Department of Physics and Astronomy. University of Missouri--Kansas City, 2021To ensure maximum circuit reliability it is very important to estimate the circuit
performance and signal integrity in the circuit design phase. A full phase simulation for
performance estimation of a large-scale circuit not only require a massive computational
resource but also need a lot of time to produce acceptable results. The estimation of
performance/signal integrity of sub-nanometer circuits mostly depends on the interconnect
capacitance. So, an accurate model for interconnect capacitance can be used in the circuit
CAD (computer-aided design) tools for circuit performance estimation before circuit
fabrication which reduces the computational resource requirement as well as the time
constraints. We propose a new capacitance models for interconnect lines in multilevel
interconnect structures by geometrically modeling the electrical flux lines of the interconnect
lines. Closed-form equations have been derived analytically for ground and coupling
capacitance. First, the capacitance model for a single line is developed, and then the new
model is used to derive expressions for the capacitance of a line surrounded by neighboring
lines in the same and the adjacent layers above and below. These expressions are simple, and
the calculated results are within 10% of Ansys Q3D extracted values.
Through silicon via (TSV) is one of the key components of the emerging 3D ICs.
However, increasing number of TSVs in smaller silicon area leads to some severe negative
impacts on the performance of the 3D IC. Growing signal integrity issues in TSVs is one of
the major challenges of 3D integration. In this paper, different materials for the cores of the
vias and the interposers are investigated to find the best possible combination that can reduce
crosstalk and other losses like return loss and insertion loss in the TSVs. We have explored
glass and silicon as interposer materials. The simulation results indicate that glass is the best
option as interposer material although silicon interposer has some distinct advantages. For
via cores three materials - copper (Cu), tungsten (W) and Cu-W bimetal are considered. From
the analysis it can concluded that W would be better for high frequency applications due to
lower transmission coefficient. Cu offers higher conductivity, but it has larger thermal
expansion coefficient mismatch with silicon. The performance of Cu-W bimetal via would be
in between Cu and W. However, W has a thermal expansion coefficient close to silicon.
Therefore, bimetal Cu-W based TSV with W as the outer layer would be a suitable option for
high frequency 3D IC. Here, we performed the analysis in terms of return loss, transmission
coefficient and crosstalk in the vias.
Signal speed in current digital systems depends mainly on the delay of interconnects.
To overcome this delay problem and keep up with Mooreโs law, 3D integrated circuit
(vertical integration of multiple dies) with through-silicon via (TSV) has been introduced to
ensure much smaller interconnect lengths, and lower delay and power consumption
compared to conventional 2D IC technology. Like 2D circuit, the estimation of 3D circuit
performance depends on different electrical parameters (capacitance, resistance, inductance)
of the TSV. So, accurate modeling of the electrical parameters of the TSV is essential for the
design and analysis of 3D ICs. We propose a set of new models to estimate the capacitance,
resistance, and inductance of a Cu-filled TSV. The proposed analytical models are derived
from the physical shape and the size of the TSV. The modeling approach is comprehensive
and includes both the cylindrical and tapered TSVs as well as the bumps.
On-chip integration of inductors has always been very challenging. However, for sub-
14nm on-chip applications, large area overhead imposed by the on-chip capacitors and
inductors has become a more severe concern. To overcome this issue and ensure power
integrity, a novel 3D Through-Silicon-Via (TSV) based inductor design is presented. The
proposed TSV based inductor has the potential to achieve both high density and high
performance. A new design of a Voltage Controlled Oscillator (VCO) utilizing the TSV
based inductor is also presented. The implementation of the VCO is intended to study the
feasibility, performance, and real-world application of the proposed TSV based inductor.Introduction -- Background of capacitance modeling of on-chip interconnect -- Accurate modeling of interconnect capacitance in multilevel interconnect structures for sub 22nm technology -- Analysis of different materials and structures for through silicon via and through glass via in 3D integrated circuits -- Impacts of different shapes of through-silicon-via core on 3D IC performance -- Accurate electrical modeling of cu-filled through-silicon-via (TSV) -- Design and characterize TSV based inductor for high frequency voltage-controlled oscillator design -- Conclusion and future wor
Distributed services across the network from edge to core
The current internet architecture is evolving from a simple carrier of bits to a platform able to provide multiple complex services running across the entire Network Service Provider (NSP) infrastructure. This calls for increased flexibility in resource management and allocation to provide dedicated, on-demand network services, leveraging a distributed infrastructure consisting of heterogeneous devices. More specifically, NSPs rely on a plethora of low-cost Customer Premise Equipment (CPE), as well as more powerful appliances at the edge of the network and in dedicated data-centers.
Currently a great research effort is spent to provide this flexibility through Fog computing, Network Functions Virtualization (NFV), and data plane programmability. Fog computing or Edge computing extends the compute and storage capabilities to the edge of the network, closer to the rapidly growing number of connected devices and applications that consume cloud services and generate massive amounts of data. A complementary technology is NFV, a network architecture concept targeting the execution of software Network Functions (NFs) in isolated Virtual Machines (VMs), potentially sharing a pool of general-purpose hosts, rather than running on dedicated hardware (i.e., appliances). Such a solution enables virtual network appliances (i.e., VMs executing network functions) to be provisioned, allocated a different amount of resources, and possibly moved across data centers in little time, which is key in ensuring that the network can keep up with the flexibility in the provisioning and deployment of virtual hosts in todayโs virtualized data centers. Moreover, recent advances in networking hardware have introduced new programmable network devices that can efficiently execute complex operations at line rate. As a result, NFs can be (partially or entirely) folded into the network, speeding up the execution of distributed services.
The work described in this Ph.D. thesis aims at showing how various network services can be deployed throughout the NSP infrastructure, accommodating to the different hardware capabilities of various appliances, by applying and extending the above-mentioned solutions. First, we consider a data center environment and the deployment of (virtualized) NFs. In this scenario, we introduce a novel methodology for the modelization of different NFs aimed at estimating their performance on different execution platforms. Moreover, we propose to extend the traditional NFV deployment outside of the data center to leverage the entire NSP infrastructure. This can be achieved by integrating native NFs, commonly available in low-cost CPEs, with an existing NFV framework. This facilitates the provision of services that require NFs close to the end user (e.g., IPsec terminator). On the other hand, resource-hungry virtualized NFs are run in the NSP data center, where they can take advantage of the superior computing and storage capabilities.
As an application, we also present a novel technique to deploy a distributed service, specifically a web filter, to leverage both the low latency of a CPE and the computational power of a data center. We then show that also the core network, today dedicated solely to packet routing, can be exploited to provide useful services. In particular, we propose a novel method to provide distributed network services in core network devices by means of task distribution and a seamless coordination among the peers involved. The aim is to transform existing network nodes (e.g., routers, switches, access points) into a highly distributed data acquisition and processing platform, which will significantly reduce the storage requirements at the Network Operations Center and the packet duplication overhead.
Finally, we propose to use new programmable network devices in data center networks to provide much needed services to distributed applications. By offloading part of the computation directly to the networking hardware, we show that it is possible to reduce both the network traffic and the overall job completion time
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