Exploration d'architectures génériques sur FPGA pour des algorithmes d'imagerie multispectrale

Les architectures multiprocesseur sur puce (MPSoC) basées sur les réseaux sur puce (NoC) constituent une des solutions les plus appropriées pour les applications embarquées temps réel de traitement du signal et de l image. De part l augmentation constante de la complexité de ces algorithmes et du type et de la taille des données manipulées, des architectures MPSoC sont nécessaires pour répondre aux contraintes de performance et de portabilité. Mais l exploration de l espace de conception de telles architectures devient très coûteuse en temps. En effet, il faut définir principalement le type et le nombre des coeurs de calcul, l architecture mémoire et le réseau de communication entre tous ces composants. La validation par simulation de haut niveau manque de précision, et la simulation de bas niveau est inadaptée au vu de la taille de l architecture. L émulation sur FPGA devient donc inévitable. Dans le domaine de l image, l imagerie spectrale est de plus en plus utilisée car elle permet de multiplier les intervalles spectraux, améliorant la définition de la lumière d une scène pour permettre un accès à des caractéristiques non visibles à l oeil nu. De nombreux paramètres modifient les caractéristiques de l algorithme, ce qui influence l architecture finale. L objectif de cette thèse est de proposer une méthode pour dimensionner au plus juste l architecture matérielle et logicielle d une application d imagerie multispectrale. La première étape est le dimensionnement du NoC en fonction du trafic sur le réseau. Le développement automatique d une plateforme d émulation sur mono ou multi FPGA facilite cette étape et détermine le positionnement des composants de calcul. Ensuite, le dimensionnement des composants de calcul et leurs fonctionnalités sont validés à l aide de plateformes de simulation existantes, avant la génération du modèle synthétisable sur FPGA. Le flot de conception est ouvert dans le sens qu il accepte différents NoC à condition d avoir le modèle source HDL de ce composant. De nombreux résultats mettent en avant les paramètres importants qui ont une influence sur les performances des architectures et du NoC en particulier. Plusieurs solutions sont décrites, commentées et critiquées. Ces travaux nous permettent de poser les premiers jalons d une plateforme d émulation complète MPSoC à base de NoCThe Multiprocessor-System-On-Chip (MPSoC) architectures based on the Network-On-Chip (NoC) communication are the one of the most appropriate solution for image and signal processing applications under real time constraints. Due to the ever increasing complexity of these algorithms, the types and sizes of the data manipulated, the MPSoC architectures are necessary to meet the constraints of performance and portability. However exploring the design space of such architecture is time consuming. Indeed, many parameters should be defined such as the type and the number of processing cores, the memory architecture and the communication network between all these components. Validation by high-level simulations has the lack of the precision. Low-level simulation is inadequate for such big size of the architecture. Therefore, the emulation on FPGA becomes inevitable. In image processing, spectral imaging is more and more used. This technology captures light from more frequencies than the human eye increasing the number of wavelengths. Invisible details can be extracted from a scene. The difference between all spectral imaging applications is the number of wavelengths and the precision. Many parameters affect the characteristics of the algorithm, having a huge impact on the final architecture. The objective of this thesis is to propose a method for sizing one of the most accurate hardware and software architecture for multispectral imaging application. The first step is the design of the NoC based on the network traffic. The automatic development of an emulation platform on a single FPGA or multi-FPGAs simplifies this step and determines the positioning of the computational components. Then, the design of computational components and their functions are validated using existing simulation platforms. The synthesizable model of the architecture on FPGA is then generated. The design flow is open. Several NoC structures can be inserted using the source model of this component. The set of results obtained points out the major parameters influencing the performances of architecture and the NoC itself. Several solutions are described and analyzed. These studies allow us to lay the groundwork for a complete MPSoC emulation platform based on NoCST ETIENNE-Bib. électronique (422189901) / SudocSudocFranceF

Estudo de Heurísticas para Mapeamento Dinâmico de Tarefas sobre a Plataforma HeMPS

Há uma tendência que sistemas intrachip multiprocessados (MPSoC) sejam compostos por dezenas ou centenas de elementos de processamento, permitindo a execução de muitas tarefas em paralelo. Assim, estratégias de alocação de recursos eficientes precisam ser desenvolvidas. Neste sentido, este trabalho investiga o desempenho das heurísticas de mapeamento de tarefas First Free, Nearest Neighbor, Path Load e Best Neighbor no MPSoC HeMPS. A heurística Best Neighbor apresentou o melhor resultado em relação à ocupação dos canais de comunicação do MPSoC, com redução de aproximadamente 32% quando comparada a heurística First Free. No entanto, essa heurística apresentou tempo de execução até 24,21% superior a heurística First Free devido à complexidade de seu algoritmo

A Simulation Tool Chain for Investigating Future V2X-based Automotive E/E Architectures

Due to the evermore rising number of functions, current E/E architectures are more and more a vulnerable source for faults and a barrier to innovation. This situation is aggravated by the integration of new technologies like Vehicle-to-X Communication (V2XC) which form the basis for a large number of future services and applications. At the same time, this “opening” of the E/E architecture to the outside world increases potential for non-deterministic disturbances. In order to overcome the limitations of current E/E architectures, application of new design principles and methodologies is necessary. Platform-based design (PBD) is a promising solution for the development of safety-critical functions, to increase reliability and to reduce development cost. Within this context, we propose a novel extensible tool chain that targets the facilitation of exploration, validation and verification of future V2X-based automotive E/E architectures. The tool chain supports composition of heterogeneous domain-specific models by integrating a heterogeneous modeling tool with a simulation middleware and serves as starting point for the investigation of PBD concepts in the V2X context. We believe that the tool chain can support modeling and validation of future V2X-based E/E architectures. In the final paper, we will evaluate the proposed approach by means of a case study regarding validation capabilities as well as execution performance

Parallele und kooperative Simulation für eingebettete Multiprozessorsysteme

Die Entwicklung von eingebetteten Systemen wird durch die stetig steigende Anzahl und Integrationsdichte neuer Funktionen in Kombination mit einem erhöhten Interaktionsgrad zunehmend zur Herausforderung. Vor diesem Hintergrund werden in dieser Arbeit Methoden zur SystemC-basierten parallelen Simulation von Multiprozessorsystemen auf Manycore Architekturen sowie zur Verbesserung der Interoperabilität zwischen heterogenen Simulationswerkzeugen entwickelt, experimentell untersucht und bewertet

Run-time management of many-core SoCs: A communication-centric approach

The single core performance hit the power and complexity limits in the beginning of this century, moving the industry towards the design of multi- and many-core system-on-chips (SoCs). The on-chip communication between the cores plays a criticalrole in the performance of these SoCs, with power dissipation, communication latency, scalability to many cores, and reliability against the transistor failures as the main design challenges. Accordingly, we dedicate this thesis to the communicationcentered management of the many-core SoCs, with the goal to advance the state-ofthe-art in addressing these challenges. To this end, we contribute to on-chip communication of many-core SoCs in three main directions. First, we start with a synthesizable SoC with full system simulation. We demonstrate the importance of the networking overhead in a practical system, and propose our sophisticated network interface (NI) that offloads the work from SW to HW. Our results show around 5x and up to 50x higher network performance, compared to previous works. As the second direction of this thesis, we study the significance of run-time application mapping. We demonstrate that contiguous application mapping not only improves the network latency (by 23%) and power dissipation (by 50%), but also improves the system throughput (by 3%) and quality-of-service (QoS) of soft real-time applications (up to 100x less deadline misses). Also our hierarchical run-time application mapping provides 99.41% successful mapping when up to 8 links are broken. As the final direction of the thesis, we propose a fault-tolerant routing algorithm, the maze-routing. It is the first-in-class algorithm that provides guaranteed delivery, a fully-distributed solution, low area overhead (by 16x), and instantaneous reconfiguration (vs. 40K cycles down time of previous works), all at the same time. Besides the individual goals of each contribution, when applicable, we ensure that our solutions scale to extreme network sizes like 12x12 and 16x16. This thesis concludes that the communication overhead and its optimization play a significant role in the performance of many-core SoC

Extra??o de dados e monitoramento de eventos na rede Intra-Chip Brnoc

With the continuous increase in transistor density in integrated circuits, circuits with greater complexity become possible, such as System on Chip (SoC). multiple microprocessors, on-chip systems with multiple processors arise Multiprocessor System-on-Chip (MPSoC). In MPSoCs, buses become a limitation, which brings us Networkon Chip intra-chip networks (NoC). The Broadcast Network on Chip (BrNoC) (WACHTER et al., 2017) is a NoC network that, being a recent one, does not yet have a specially developed debugging tool. In this work, the objective was to implement a graphical interface for monitoring events in simulations of the BrNoC network, in order to contribute to the study of intra-chip networks with Broadcast support. Among the activities carried out in the development of the work are: the instrumentation of the code in the Hardware description layer with mechanisms for extracting data and capturing events; the definition of a communication standard between the tool layers; and the availability of a graphical interface for analyzing the information collected. As a result of the proposed implementation, it can be observed that, despite its simplicity, it ends up being robust, as it does not ignore any signal and operates, regardless of the state of the router?s state machines, collecting the signals that have changed values, thus allowing , monitor the entire state of the networkanditsrouters. Regardingsimulationperformance,itisobservedthatthereisanaverage increase in simulation time between 22.6% and 34.1%.Com o aumento cont?nuo da densidade de transistores nos circuitos integrados, circuitos com maiorcomplexidadesetornamposs?veis,taiscomoosSystemonChip(SistemaemChip)(SoC). Com o crescimento da exig?ncia por dispositivos mais complexos e o avan?o da fabrica??o de chips com m?ltiplos microprocessadores, surgem os sistemas em chip com m?ltiplos proces- sadores Multiprocessor System-on-Chip (Sistema Multiprocessado em Chip) (MPSoC). Nos MPSoCs, os barramentos se tornam uma limita??o, o que nos tr?s as redes intra-chip Network on Chip (Rede Intra-chip) (NoC). A Broadcast Network on Chip (Rede de Broadcast Intra-chip) (BrNoC) (WACHTER et al., 2017) ? uma rede NoC que, por ser um recente, ainda n?o conta com uma ferramenta de depura??o especialmente desenvolvida. Neste trabalho o objetivo foi a implementa??o de uma interface gr?fica para o acompanhamento de eventos em simula??es da rede BrNoC a fim de contribuir para o estudo de redes intra-chip com suporte a broadcast. Entre as atividades realizadas no desenvolvimento do trabalho est?o: a instrumentaliza??o do c?digo na camada de descri??o Hardware com mecanismos de extra??o dos dados e de captura deeventos; adefini??o deumpadr?odecomunica??o entreascamadasdaferramenta; ea dispo- nibilidadedeumainterfacegr?ficaparaan?lisesdasinforma??escoletadas. Comoresultadosda implementa??oproposta,pode-seobservarque,apesardasimplicidade,elaacabasendorobusta, por n?o ignorar nenhum sinal e operar, independentemente, do estado das m?quinas de estado do roteador, coletando os sinais que tiverem valores alterados, permitindo assim, acompanhar todo o estado da rede e seus roteadores. Em rela??o ao desempenho da simula??o, observa-se que houve um aumento m?dio no tempo de simula??o entre 22.6% e 34.1%