Composition and synchronization of real-time components upon one processor

Many industrial systems have various hardware and software functions for controlling mechanics. If these functions act independently, as they do in legacy situations, their overall performance is not optimal. There is a trend towards optimizing the overall system performance and creating a synergy between the different functions in a system, which is achieved by replacing more and more dedicated, single-function hardware by software components running on programmable platforms. This increases the re-usability of the functions, but their synergy requires also that (parts of) the multiple software functions share the same embedded platform. In this work, we look at the composition of inter-dependent software functions on a shared platform from a timing perspective. We consider platforms comprised of one preemptive processor resource and, optionally, multiple non-preemptive resources. Each function is implemented by a set of tasks; the group of tasks of a function that executes on the same processor, along with its scheduler, is called a component. The tasks of a component typically have hard timing constraints. Fulfilling these timing constraints of a component requires analysis. Looking at a single function, co-operative scheduling of the tasks within a component has already proven to be a powerful tool to make the implementation of a function more predictable. For example, co-operative scheduling can accelerate the execution of a task (making it easier to satisfy timing constraints), it can reduce the cost of arbitrary preemptions (leading to more realistic execution-time estimates) and it can guarantee access to other resources without the need for arbitration by other protocols. Since timeliness is an important functional requirement, (re-)use of a component for composition and integration on a platform must deal with timing. To enable us to analyze and specify the timing requirements of a particular component in isolation from other components, we reserve and enforce the availability of all its specified resources during run-time. The real-time systems community has proposed hierarchical scheduling frameworks (HSFs) to implement this isolation between components. After admitting a component on a shared platform, a component in an HSF keeps meeting its timing constraints as long as it behaves as specified. If it violates its specification, it may be penalized, but other components are temporally isolated from the malignant effects. A component in an HSF is said to execute on a virtual platform with a dedicated processor at a speed proportional to its reserved processor supply. Three effects disturb this point of view. Firstly, processor time is supplied discontinuously. Secondly, the actual processor is faster. Thirdly, the HSF no longer guarantees the isolation of an individual component when two arbitrary components violate their specification during access to non-preemptive resources, even when access is arbitrated via well-defined real-time protocols. The scientific contributions of this work focus on these three issues. Our solutions to these issues cover the system design from component requirements to run-time allocation. Firstly, we present a novel scheduling method that enables us to integrate the component into an HSF. It guarantees that each integrated component executes its tasks exactly in the same order regardless of a continuous or a discontinuous supply of processor time. Using our method, the component executes on a virtual platform and it only experiences that the processor speed is different from the actual processor speed. As a result, we can focus on the traditional scheduling problem of meeting deadline constraints of tasks on a uni-processor platform. For such platforms, we show how scheduling tasks co-operatively within a component helps to meet the deadlines of this component. We compare the strength of these cooperative scheduling techniques to theoretically optimal schedulers. Secondly, we standardize the way of computing the resource requirements of a component, even in the presence of non-preemptive resources. We can therefore apply the same timing analysis to the components in an HSF as to the tasks inside, regardless of their scheduling or their protocol being used for non-preemptive resources. This increases the re-usability of the timing analysis of components. We also make non-preemptive resources transparent during the development cycle of a component, i.e., the developer of a component can be unaware of the actual protocol being used in an HSF. Components can therefore be unaware that access to non-preemptive resources requires arbitration. Finally, we complement the existing real-time protocols for arbitrating access to non-preemptive resources with mechanisms to confine temporal faults to those components in the HSF that share the same non-preemptive resources. We compare the overheads of sharing non-preemptive resources between components with and without mechanisms for confinement of temporal faults. We do this by means of experiments within an HSF-enabled real-time operating system

FPGA-plattform för bildbehandling

I denna licentiatavhandling i automationsteknik planeras, förverkligas och testas en FPGA-plattform för bildbehandling, som fungerar som en bildbehandlingsserver på Ethernet och Internet. Plattformen kan utföra ett stort antal databehandlingsmetoder och -tillämpningar inom höghastighetskommunikation i realtid. Med hjälp av Altera- och Eclipse-verktygen, Terasics ALTERA DE3-utvecklingskort med Alteras Stratix III FPGA och HSMC-NET- och minneskort och VHDL-, Verilog-, C- och Assembler-programmeringsspråket skapas en 1 Gbps FPGA-plattform för bildbehandling. Vidare behandlas till lösningen hörande begrepp, som en FPGA-plattform som ett inbyggt system, orsak till val av FPGA-hårdvara och förväntningarna på ett utvecklingskort. Viktiga verktyg, hjälpmedel och komponenter vid konstruktion av en bildbehandlingsplattform samt möjligheter för pipeline och parallellism kartläggs. Konstruktions- och implementeringsmetoder vid planering och konstruktion av hårdvara och mjukvara presenteras speciellt gränssnitt mellan hårdvara och mjukvara och deras verktygs roller i ett HW/SW Co-Design-system. Implementering av hårdvara och mjukvara, hårdvaran, moder-, dotter- och minneskortet med sammankopplingar och implementerade funktioner beskrivs. Mjukvaran beskrivs med implementerade mjukvarufunktionsgrupper såsom system start-up-, operativsystem-, bildbehandlings- och avbrottsrutiner. Det utfördes manuella och prestandatester med plattformen. De manuella TCP- och UDP-testerna visar att alla kommandon och operationer fungerar korrekt i alla lager och på alla nivåer. Prestandatesterna visar att plattformen kan hantera både låg- och högbelastande TCP- och UDP-trafik med stigande och sjunkande längd på testdata. Alla tester visar samma struktur och trend för genomströmning. Maximigenomströmningen för plattformen är ca 7,5 Mbps med en Nios II/f-processor och arbetsfrekvens på 50 MHz. Mitt bidrag har varit att bygga en mer omfattande funktionell mjukvara med hjälp av basprogramvara samt att bygga en omfattande funktionell hårdvara i IPS. Dessutom att bygga en omfattande funktionell testprogramvara för PC – alla med nödvändiga funktioner och komponenter.fi=Opinnäytetyö kokotekstinä PDF-muodossa.|en=Thesis fulltext in PDF format.|sv=Lärdomsprov tillgängligt som fulltext i PDF-format

Fundamentals

Volume 1 establishes the foundations of this new field. It goes through all the steps from data collection, their summary and clustering, to different aspects of resource-aware learning, i.e., hardware, memory, energy, and communication awareness. Machine learning methods are inspected with respect to resource requirements and how to enhance scalability on diverse computing architectures ranging from embedded systems to large computing clusters

Fundamentals

Volume 1 establishes the foundations of this new field. It goes through all the steps from data collection, their summary and clustering, to different aspects of resource-aware learning, i.e., hardware, memory, energy, and communication awareness. Machine learning methods are inspected with respect to resource requirements and how to enhance scalability on diverse computing architectures ranging from embedded systems to large computing clusters

A Problem-Oriented Approach for Dynamic Verification of Heterogeneous Embedded Systems

This work presents a virtual prototyping methodology for the design and verification of industrial devices in the field level of industrial automation systems. This work demonstrates that virtual prototypes can help increase the confidence in the correctness of a design thanks to a deeper understanding of the complex interactions between hardware, software, analog and mixed-signal components of embedded systems and the physical processes they interact with