Bit plane slicing technique to classify date varieties

Varietal purity is an important parameter in the quality standards of dates. In general, variety identification is done by visual inspection method in grading and handling facilities. Online variety assessment using computer vision methods with minimum features and fast image processing and classification algorithms would be highly beneficial for the date industry. Three date varieties (Khalas, Fard and Madina) were classified using a single type of feature, Euler number, used on the eight bit planes available from gray scale images. An overall classification accuracy of 91.5% was achieved using a two layer neural network classifier with hyperbolic tangent sigmoid transfer function. Additionally, image segmentation was performed using the two most significant bit planes. Therefore, a complete feature extraction module based on logic values and morphological image processing as proposed here can be easily implemented in hardware

Medición de diferencia de fase entre señales utilizando FPGAs

Este Trabajo Fin de Grado consiste en el diseño y desarrollo de un circuito prototipo en una FPGA, para medir la diferencia de fase que se genera entre dos señales. El trabajo se ha desarrollado utilizando una tarjeta de evaluación Digilent Nexys 3, la cual utiliza una FPGA Spartan-6 de Xilinx. Para diseñar e implementar los circuitos sobre la FPGA se ha utilizado el entorno de desarrollo Xilinx ISE Design Suite, que permite la síntesis y análisis de diseños HDL o la realización de simulaciones. Además, VHDL ha sido el lenguaje seleccionado para la realización del trabajo. El sistema completo pretende utilizar una FPGA para medir el desfase de dos señales, así como la realización de un módulo de test encargado de generar las señales que serán utilizadas para comprobar el correcto funcionamiento del sistema. Este módulo de test permite seleccionar el desfase deseado, con una precisión de 10ns, para dos señales de 160ns de período. El medidor de fase consiste en una compuerta XOR y un contador de pulsos. El reloj utilizado por el contador es el reloj interno de la Nexys 3, que tiene una frecuencia de 100MHz, por lo tanto, la precisión del sistema medidor de fase es de 10ns. Los resultados de las medidas se muestran al usuario mediante la utilización de los displays 7-segmentos que vienen integrados en la propia tarjeta de evaluación. Las pruebas realizadas utilizando el módulo de test concluyen que el sistema funciona de forma correcta, aunque queda pendiente la realización de pruebas más exhaustivas. Tanto el desarrollo de este sistema como los resultados obtenidos se exponen a lo largo de los capítulos de esta memoria. Se proponen además varias soluciones como trabajo futuro

SSI Dividing Numerical Integrator

Práce se zabývá numerickou integrací a operací dělení v hardware. Čtenář je seznámen s numerickým řešením diferenciálních rovnic pomocí několika různých metod, z nichž lze zmínit například Taylorovu řadu. Dále je probrána operace dělení v hardware a způsob jejího provedení v FPGA. Následně je navržen paralelně-paralelní a sériově-paralelní integrátor. Praktickým cílem práce je návrh a implementace sériově-sériového dělícího integrátoru a vytvoření simulátoru pro něj.The thesis deals with numerical integration and hardware division operations. The reader is familiar with the numerical solution of differential equations through several different methods, for example Taylor's series. Furthermore, it is discussed the operation of division in the hardware and the method of its implementation in the FPGA. Subsequently, a parallel-parallel and serial-parallel integrator is designed. The practical aim of the thesis is to design and implement a serial-serial dividing integrator and create a simulator for it. 

On the use of inexact, pruned hardware in atmospheric modelling

Inexact hardware design, which advocates trading the accuracy of computations in exchange for significant savings in area, power and/or performance of computing hardware, has received increasing prominence in several error-tolerant application domains, particularly those involving perceptual or statistical end-users. In this paper, we evaluate inexact hardware for its applicability in weather and climate modelling. We expand previous studies on inexact techniques, in particular probabilistic pruning, to floating point arithmetic units and derive several simulated setups of pruned hardware with reasonable levels of error for applications in atmospheric modelling. The setup is tested on the Lorenz ‘96 model, a toy model for atmospheric dynamics, using software emulation for the proposed hardware. The results show that large parts of the computation tolerate the use of pruned hardware blocks without major changes in the quality of short- and long-time diagnostics, such as forecast errors and probability density functions. This could open the door to significant savings in computational cost and to higher resolution simulations with weather and climate models

Análisis de temperatura en FPGAs

Este proyecto se ha basado fundamentalmente en el diseño, desarrollo y caracterización de osciladores anillo en una FPGA, modelo Virtex-5 para obtener la temperatura de la misma a través de la frecuencia de oscilación de los sensores. Para ello primero se diseñaron los osciladores anillo en VHDL y una lógica de control que permitiera obtener la frecuencia de oscilación y controlase la habilitación/deshabilitación de los sensores. Los datos de la frecuencia obtenidos fueron enviados a través de la interfaz RS232 (UART) al ordenador. Con el fin de almacenar y procesar esos datos se crea una interfaz en Matlab. Tras obtener los datos se realizaron distintas representaciones gráficas para ayudar a la interpretación de los resultados. Con el fin de obtener la temperatura de la placa y poder así realizar la calibración de los sensores anillo, se monitorizó el diodo interno de temperatura pre-calibrado que posee el modelo de FPGA utilizado. Por tal razón, el módulo System Monitor tuvo que ser considerado como parte de nuestro diseño obteniendo aproximadamente la temperatura del FPGA como su respectivo voltaje de núcleo Una vez definido el oscilador e interconectarlo con Matlab, se procedió a realizar tres experimentos diferentes: El primero consistió en identificar el número de inversores que son necesarios para que los datos recogidos del sensor anillo sean los más fieles posibles a la realidad. En el segundo se realizó la calibración de dos sensores próximos al diodo calibrado interno que posee el FPGA para estudiar cual es la variación de la frecuencia de oscilación con respecto el voltaje de núcleo, la temperatura y la posición de los anillos. Y el tercero consistió en colocar 48 sensores distribuidos por toda la FPGA y obtener la frecuencia de oscilación de cada uno de ellos, procesando un número determinado de muestras por cada sensor. En resumen, se han realizado 12 versiones de circuitos sobre los cuales se han hecho 21.504 medidas. Y el código contiene unas 8.700 líneas divididas en 6 ficheros diferentes.The aim of this project tackles the design, development and analysis of ring oscillators, which comprises of a series of inverters, implemented over an FPGA-Virtex-5 in order to sense the temperature gradient of hot-spots in FPGAs. Therefore, our proposal consists of designing an array of ring oscillators which are monitored by a control central unit which actives the period required to conduct several stages of our design in order to read the counter generated by ring oscillator. The data obtained are computationally processed carrying out varies operations such as frequency oscillation calculation, median and standard deviation as well as several graphs depicting profiles thermal. Likewise, a PC connected via UART to the FPGA in charges of receiving the data from our design. In order to get the absolute temperature of the tested FPGA and be able to perform calibration of the sensor ring the System Monitor module was used. It’s worth mentioning that this Xilinx FPGA contains a pre-calibrated built-in thermal diode which is sensed by the module indicated earlier. Several experiments were carried out evaluating the ring oscillator design. It can be mentioned the following: As a first experiment, it was examined the number of inverters utilized in each sensor by means of several design combinations and evaluated their respective sensor performance. As second one, it was calibrated two ring oscillator sensors closets to the position of the built-in thermal diode in order to evaluate the variation of the tuned frequency related to absolute temperature, voltage core and relative placement within FPGA. Lastly, it was tested the frequency oscillation of each sensor considering an array of 48 thermal sensors distributed properly over the FPGA. In summary, there have been made 12 circuit versions and 21.504 measurements. And the code contains 8.700 lines divided into 6 different files

VLSI architectures for mean-shift based object tracking

The demand for real-time video surveillance systems is increasing rapidly. The purpose of these systems includes surveillance as well as monitoring and controlling the events. Today there are several real-time computer vision applications based on image understanding which emulate the human vision and intelligence. These machines include object tracking as their primary task. Object tracking refers to estimating the trajectory of an object of interest in a video. A tracking system works on the principle of video processing algorithms. Video processing includes a huge amount of data to be processed and this fact dictates while implementing the algorithms on any hardware. An efficient video processing algorithm is adopted here for estimating the trajectory of moving objects in a video. The tracking algorithm is based on mean-shift iteration technique. This method tracks accurately the target object in a sequence of video frames. The key objective is to implement the algorithm on an FPGA platform with less computational complexity and hardware utilization for real-time applications. Two VLSI architectures for the mean-shift based object tracking system are implemented and verified. The FPGA target device used here is XILINX xc5vlx110t. The architectures consist of many divider modules which plays a significant role in the performance of the system. Divider includes shifting and addition operations repeatedly to get a particular result. Hence emphasis should be given for the design of an optimized divider unit. Here a serial divider using non-restoring algorithm is implemented in 90 nm technology using CADENCE tool

Generación de falsas claves criptográficas como medida de protección frente a ataques por canal lateral

In the late 90s, Paul C. Kocher introduced the concept of differential attack focused on the power consumption of a cryptographic device. In this type of analysis the plain text sent to the device is known, and all possible hypotheses of a subset of the key, related to a specific point of the cryptographic algorithm, are tested. If the key value at that point depends only on 1 byte, it is possible to predict the input current based on a theoretical model of power consumption. Thus, using statistic procedures, it is easy to compare the consumption measured during the processing of each plain text and the intermediate values related to all the hypothesis of the key.The one with the highest level of similarity will correspond to the actual key. So far the countermeasures proposed to prevent the success of the attack can be classified into two groups: Masking and Hiding. Masking tries to decouple the processed data and the power consumption by adding a random mask which is unknown by the attacker. Therefore, it is impossible to make a hypothesis that allows the theoretical and the real power consumption of the device to be related. Although is a valid method, the key could be revealed by performing a second-order attack that analyzes several points of the current trace. Hiding aims at making constant the consumption of a device in each clock cycle and independent of the processed data. In order to achieve this objective, the data is processed in double line, in such a way that the datum and its complementary are processed together, so that the same number of transitions always occur on every clock cycle. The weakness of such a method lies on the impossibility of building identical CMOS cells, which causes a minimum difference of consumption between the two lines that can be used successfully to discover the key. This thesis proposes a countermeasure based on a differentiated protection strategy with respect to the proposals made in other specific studies. It is intended to modify the algorithm in order to force a very high correlation with a different hypothesis to the one of the true key (Faking). Thus, the actual key is hidden behind the strong correlation, which is impossible to differentiate from the rest of false assumptions and remains protected. To verify its performance a trial bank has been designed to launch consumption analysis attacks. We have implemented the algorithm AES due to its simplicity and strength. Two types of attacks have been carried out. In the first one, the analysis was performed using both the correlation and the mean difference analysis without including any countermeasure. In the second attack, the proposed countermeasure has been added and the attack was repeated to check its effectiveness. We have evaluated three different situations. First of all, the algorithm and the countermeasure are solved by software on a 32-bit processor. Secondly, the algorithm is executed in software and the implementation of the countermeasure has been performed with a specific hardware coprocessor. Finally, a full hardware implementation including both the algorithm and the countermeasure has been chosen.All of them have been implemented on a Virtex 5 FPGA Xilinx. Several conclusions are obtained from the comparison between each of the AES implementations without countermeasures and their respective solution with the added countermeasure. The obtained results are also compared to other which use "masking" and "hiding" techniques. The results demonstrate that the proposal is valid. In all three cases, the protected system behaves like the unprotected system but returning the false key after the attacks. It should be noted that the amount of resources needed to carry out the "Faking" is less than the "Masking" or "Hiding" and the time needed to process the plain text is not particularly affected.A finales de los 90 Paul C.Kocher introdujo por primera vez el concepto de ataque diferencial sobre el consumo de corriente de un dispositivo criptográfico. En este tipo de análisis, se conoce el texto plano que se envía al dispositivo y se plantean todas las posibles hipótesis de la clave para un punto concreto del algoritmo. Si el valor en ese punto del algoritmo depende únicamente de 1 byte de la clave, es posible calcular todos los valores que se producirán. Llegado a este punto, se compara, por métodos estadísticos, el consumo medido durante el procesado de cada texto plano y los valores intermedios relacionados con todas las hipótesis de la clave. Aquella que mayor nivel de similitud tenga corresponderá con la clave real. Las contramedidas propuestas hasta la fecha, para evitar el éxito del ata-que, pueden separarse en dos grupos: enmascaramiento (Masking) y ocultación (Hiding). El enmascaramiento trata de desvincular el dato procesado del consumo eléctrico mediante la adición de una máscara aleatoria y desconocida por el atacante. En consecuencia, resulta imposible realizar una hipótesis que permita relacionar los consumos teórico y real del dispositivo. Si bien este es un método inicialmente válido, puede descubrirse la clave realizando un ataque de segundo orden que analiza varios puntos del consumo. La ocultación persigue que el consumo de un dispositivo sea el mismo en cada ciclo de reloj e independiente del dato procesado. Para ello, se procesa el dato en doble línea, por un lado el dato propiamente dicho y por el otro su complementario, de forma que siempre se produzcan la misma cantidad de transiciones en cada ciclo de reloj. La debilidad de este método radica en la práctica imposibilidad de construir celdas CMOS idénticas, esto provoca que siempre exista una diferencia de consumo entre las dos líneas y pueda usarse con éxito para descubrir la clave. En esta tesis se propone una contramedida basada en una estrategia de protección claramente diferenciada con respecto a las propuestas realizadas en la bibliografía específica. Se pretende modificar el algoritmo con el objetivo de forzar una correlación muy alta en una hipótesis diferente a la de la clave (Faking). De este modo, la clave real se oculta tras la fuerte correlación aparecida, resulta imposible diferenciarla del resto de hipótesis falsas y queda protegida. Para verificar su funcionamiento se ha montado un banco de pruebas para realizar ataques por análisis de consumo. Se ha implementado el algoritmo AES debido a su simplicidad y robustez. Se han realizado dos tipos de ataques: en el primero se han practicado análisis de correlación y diferencia de medias sin contramedida alguna; en el segundo, se ha añadido la contramedida y se han repetido los ataques para comprobar su eficacia. Se han evaluado 3 escenarios diferentes, primeramente el algoritmo y la contramedida se resuelven mediante software en un procesador de 32 bits. En segundo lugar, el algoritmo se resuelve mediante software y la implementación de la contramedida se ha realizado en un coprocesador hardware específico. Fi-nalmente, se ha elegido una implementación totalmente hardware para resolver tanto el algoritmo como la contramedida. Todos ellos se han implementado sobre una FPGA Virtex5 de Xilinx. Las conclusiones se obtienen de la comparación entre cada una de las im-plementaciones del AES sin contramedidas y su respectiva solución con la con-tramedida añadida. También se comparan los resultados obtenidos con otros que utilizan las técnicas "Masking" y "Hiding" Los resultados demuestran que la propuesta es válida. En los tres casos, el sistema protegido se comporta igual que el sistema sin proteger, pero retornando la clave falsa ante los ataques realizados. Se ha de destacar que, la cantidad de recursos necesarios para llevar a cabo el "Faking" es menor que con el "Masking" o el "Hiding" y el tiempo necesario para procesar el texto plano no se ve particularmente afectado por su inclusión

Simulation of the upgraded Phase-1 Trigger Readout Electronics of the Liquid-Argon Calorimeter of the ATLAS Detector at the LHC

In the context of an intensive upgrade plan for the Large Hadron Collider (LHC) in order to provide proton beams of increased luminosity, a revision of the data readout electronics of the Liquid-Argon-Calorimeter of the ATLAS detector is scheduled. This is required to retain the efficiency of the trigger at increased event rates despite its fixed bandwidth. The focus lies on the early digitization and finer segmentation of the data provided to the trigger. Furthermore, there is the possibility to implement new energy reconstruction algorithms which are adapted to the specific requirements of the trigger. In order to constitute crucial design decisions, such as the digitization scale or the choice of digital signal processing algorithms, comprehensive simulations are required. High trigger efficiencies are decisive at it for the successful continuation of the measurements of rare StandardModel processes as well as for a high sensitivity to new physics beyond the established theories. It can be shown that a significantly improved resolution of the missing transverse energy calculated by the trigger is achievable due to the revised segmentation of the data. Various energy reconstruction algorithms are investigated in detail. It can be concluded that these will facilitate reliable trigger decisions for all expected working conditions and for the whole possible energy range

Sustainable Trusted Computing: A Novel Approach for a Flexible and Secure Update of Cryptographic Engines on a Trusted Platform Module

Trusted computing is gaining an increasing acceptance in the industry and finding its way to cloud computing. With this penetration, the question arises whether the concept of hardwired security modules will cope with the increasing sophistication and security requirements of future IT systems and the ever expanding threats and violations. So far, embedding cryptographic hardware engines into the Trusted Platform Module (TPM) has been regarded as a security feature. However, new developments in cryptanalysis, side-channel analysis, and the emergence of novel powerful computing systems, such as quantum computers, can render this approach useless. Given that, the question arises: Do we have to throw away all TPMs and lose the data protected by them, if someday a cryptographic engine on the TPM becomes insecure? To address this question, we present a novel architecture called Sustainable Trusted Platform Module (STPM), which guarantees a secure update of the TPM cryptographic engines without compromising the system’s trustworthiness. The STPM architecture has been implemented as a proof-of-concept on top of a Xilinx Virtex-5 FPGA platform, demonstrating the test cases with an update of the fundamental hash and asymmetric engines of the TPM