Broadband Receiver Electronic Circuits for Fiber-Optical Communication Systems

The exponential growth of internet traffic drives datacenters to constantly improve their capacity. As the copper based network infrastructure is being replaced by fiber-optical interconnects, new industrial standards for higher datarates are required. Several research and industrial organizations are aiming towards 400 Gb Ethernet and beyond, which brings new challenges to the field of high-speed broadband electronic circuit design. Replacing OOK with higher M-ary modulation formats and using higher datarates increases network capacity but at the cost of power. With datacenters rapidly becoming significant energy consumers on the global scale, the energy efficiency of the optical interconnect transceivers takes a primary role in the development of novel systems. There are several additional challenges unique in the design of a broadband shortreach fiber-optical receiver system. The sensitivity of the receiver depends on the noise performance of the PD and the electronics. The overall system noise must be optimized for the specific application, modulation scheme, PD and VCSEL characteristics. The topology of the transimpedance amplifier affects the noise and frequency response of the PD, so the system must be optimized as a whole. Most state-of-the-art receivers are built on high-end semiconductor SiGe and InP technologies. However, there are still several design decisions to be made in order to get low noise, high energy efficiency and adequate bandwidth. In order to overcome the frequency limitations of the optoelectronic components, bandwidth enhancement and channel equalization techniques are used. In this work several different blocks of a receiver system are designed and characterized. A broadband, 50 GHz bandwidth CB-based TIA and a tunable gain equalizer are designed in a 130 nm SiGe BiCMOS process. An ultra-broadband traveling wave amplifier is presented, based on a 250 nm InP DHBT technology demonstrating a 207 GHz bandwidth. Two TIA front-end topologies with 133 GHz bandwidth, a CB and a CE with shunt-shunt feedback, based on a 130 nm InP DHBT technology are designed and compared

High-speed electronics for silicon photonics transceivers

High-speed electronic integrated circuits are essential to the development of new fiber-optic communication systems. As a consequence of the increasing speeds and multi-channel operation, close integration and co-design of photonic and electronic devices have become a necessity to realize high-performance sub-systems. Such co-design on the other hand also enables the design of new electro-optic architectures to create and process multi-level optical signals. This presentation will illustrate a number of recent and ongoing developments in IDLab, an imec research group, from various H2020 projects with a focus on application-specific high-speed electronic transceiver circuits such as driver amplifiers and transimpedance amplifiers (TIAs)

Multichannel 25 Gb/s low-power driver and transimpedance amplifier integrated circuits for 100 Gb/s optical links

Highly integrated electronic driver and receiver ICs with low-power consumption are essential for the development of cost-effective multichannel fiber-optic transceivers with small form factor. This paper presents the latest results of a two-channel 28 Gb/s driver array for optical duobinary modulation and a four-channel 25 Gb/s TIA array suited for both NRZ and optical duobinary detection. This paper demonstrated that 28 Gb/s duobinary signals can be efficiently generated on chip with a delay-and-add digital filter and that the driver power consumption can be significantly reduced by optimizing the drive impedance well above 50 Omega, without degrading the signal quality. To the best of our knowledge, this is the fastest modulator driver with on-chip duobinary encoding and precoding, consuming only 652 mW per channel at a differential output swing of 6 Vpp. The 4 x 25 Gb/s TIA shows a good sensitivity of - 10.3 dBm average optical input power at 25 Gb/s for PRBS 2(31) -1 and low power consumption of 77 mW per channel. Both ICs were developed in a 130 nm SiGe BiCMOS process

Electronic-photonic board as an integration platform for Tb/s multi-chip optical communication

Chip-on-board silicon photonics O-band wavelength-division multiplexing transceivers have been developed that will eventually enable high-throughput on-board optical communication for multi-socket on-board communication. This direct, any-to-any configuration yields low-latency, low-power optical communication among multiple compute nodes on the board. Silicon photonic transceiver chips are flip-chipped on a polymer waveguide containing an electro-optical circuit board using adiabatic coupling and then completed with driver and amplifier electronic chips. A transceiver assembly based on wire-bond technology verifies 50 Gb/s operation per channel, and the flip-chip version demonstrates the chip on-board assembly techniques for compact on-board transceivers

A 40 Gb/s chip-to-chip interconnect for 8-socket direct connectivity using integrated photonics

We present an O-band any-to-any chip-to-chip (C2C) interconnection at 40 Gb/s suitable for up to 8-socket direct connectivity in multi-socket server boards, utilizing integrated low-energy photonics for the transceiver and routing functions. The C2C interconnect exploits an Si-based ring modulator as its transmitter and a co-packaged photodiode/transimpedance amplifier enabled receiver interconnected over an 8 x 8 Si-based arrayed waveguide grating router, allowing for a single-hop flat-topology interconnection between eight nodes. A proof-of-concept demonstration of the C2C interconnect is presented at 25 and 40 Gb/s for eight possible routing scenarios, revealing clear eye diagrams at both data rates with extinction ratios of 4.8 +/- 0.3 and 4.38 +/- 0.31 dB, respectively, among the eight routed signals

A 10-Meter Active Optical Cable Utilizing POF With 4 × 10-Gb/s CMOS Transceiver Chipsets

This paper presents a 10-m active optical cable (AOC) utilizing a graded-index plastic optical fiber (POF) for HDMI applications, where 4-channel 10-Gb/s/ch transceiver chipsets were implemented in 0.13-μm CMOS process and integrated upon a FR4 PC-board within pluggable connectors. Passive optical alignment comprising optical devices, optical subassembly, and POF was precisely located within the tolerance range of +/-10 μm, leading to successful mass-production. The transmitter (Tx) includes a VCSEL driver exploiting equalization and feedforward pre-emphasis to support 10-Gb/s data modulation. Also, a novel input data detector is proposed to turn on/off VCSEL diodes automatically for longer sustainability and lower power consumption. The receiver (Rx) employs a double-gain feedforward transimpedance amplifier followed by a selectable two-stage equalizer to choose either 6-Gb/s or 10-Gb/s operations, depending upon the specified HDMI applications. Also, a simple dc offset current cancellation and a novel monitor circuit are proposed for stable biasing and to keep tracking the average photocurrent of each photodiode. Measured results of Tx demonstrate 5.6-mA bias currents and 6.0-mAPP modulation currents, consuming 21.25 mA in maximum, whereas Rx provides 56.7-dBΩ transimpedance gain, 6-GHz bandwidth, and -10.4-dBm optical sensitivity for 10 -12 BER with 21.2 mA current consumption. The 10-meter POF AOC demonstrates wide and clean eye-diagrams up to 10 Gb/s, successfully showing 8-Mpixel 60-fps video data stream

Photonic integration enabling new multiplexing concepts in optical board-to-board and rack-to-rack interconnects

New broadband applications are causing the datacenters to proliferate, raising the bar for higher interconnection speeds. So far, optical board-to-board and rack-to-rack interconnects relied primarily on low-cost commodity optical components assembled in a single package. Although this concept proved successful in the first generations of optical-interconnect modules, scalability is a daunting issue as signaling rates extend beyond 25 Gb/s. In this paper we present our work towards the development of two technology platforms for migration beyond Infiniband enhanced data rate (EDR), introducing new concepts in board-to-board and rack-to-rack interconnects. The first platform is developed in the framework of MIRAGE European project and relies on proven VCSEL technology, exploiting the inherent cost, yield, reliability and power consumption advantages of VCSELs. Wavelength multiplexing, PAM-4 modulation and multi-core fiber (MCF) multiplexing are introduced by combining VCSELs with integrated Si and glass photonics as well as BiCMOS electronics. An in-plane MCF-to-SOI interface is demonstrated, allowing coupling from the MCF cores to 340x400 nm Si waveguides. Development of a low-power VCSEL driver with integrated feed-forward equalizer is reported, allowing PAM-4 modulation of a bandwidth-limited VCSEL beyond 25 Gbaud. The second platform, developed within the frames of the European project PHOXTROT, considers the use of modulation formats of increased complexity in the context of optical interconnects. Powered by the evolution of DSP technology and towards an integration path between inter and intra datacenter traffic, this platform investigates optical interconnection system concepts capable to support 16QAM 40GBd data traffic, exploiting the advancements of silicon and polymer technologies

Optoelectronic devices and packaging for information photonics

This thesis studies optoelectronic devices and the integration of these components onto optoelectronic multi chip modules (OE-MCMs) using a combination of packaging techniques. For this project, (1×12) array photodetectors were developed using PIN diodes with a GaAs/AlGaAs strained layer structure. The devices had a pitch of 250μm, operated at a wavelength of 850nm. Optical characterisation experiments of two types of detector arrays (shoe and ring) were successfully performed. Overall, the shoe devices achieved more consistent results in comparison with ring diodes, i.e. lower dark current and series resistance values. A decision was made to choose the shoe design for implementation into the high speed systems demonstrator. The (1x12) VCSEL array devices were the optical sources used in my research. This was an identical array at 250μm pitch configuration used in order to match the photodetector array. These devices had a wavelength of 850nm. Optoelectronic testing of the VCSEL was successfully conducted, which provided good beam profile analysis and I-V-P measurements of the VCSEL array. This was then implemented into a simple demonstrator system, where eye diagrams examined the systems performance and characteristics of the full system and showed positive results. An explanation was given of the following optoelectronic bonding techniques: Wire bonding and flip chip bonding with its associated technologies, i.e. Solder, gold stud bump and ACF. Also, technologies, such as ultrasonic flip chip bonding and gold micro-post technology were looked into and discussed. Experimental work implementing these methods on packaging the optoelectronic devices was successfully conducted and described in detail. Packaging of the optoelectronic devices onto the OEMCM was successfully performed. Electrical tests were successfully carried out on the flip chip bonded VCSEL and Photodetector arrays. These results verified that the devices attached on the MCM achieved good electrical performance and reliable bonding. Finally, preliminary testing was conducted on the fully assembled OE-MCMs. The aim was to initially power up the mixed signal chip (VCSEL driver), and then observe the VCSEL output