Formal Model Engineering for Embedded Systems Using Real-Time Maude

This paper motivates why Real-Time Maude should be well suited to provide a formal semantics and formal analysis capabilities to modeling languages for embedded systems. One can then use the code generation facilities of the tools for the modeling languages to automatically synthesize Real-Time Maude verification models from design models, enabling a formal model engineering process that combines the convenience of modeling using an informal but intuitive modeling language with formal verification. We give a brief overview six fairly different modeling formalisms for which Real-Time Maude has provided the formal semantics and (possibly) formal analysis. These models include behavioral subsets of the avionics modeling standard AADL, Ptolemy II discrete-event models, two EMF-based timed model transformation systems, and a modeling language for handset software.Comment: In Proceedings AMMSE 2011, arXiv:1106.596

Timed Chi: Modeling, Simulation and Verification of Hardware Systems

Timed Chi (chi) is a timed process algebra, designed for Modeling, simulation, verification and real-time control. Its application domain consists of large and complex manufacturing systems. The straightforward syntax and semantics are also highly suited to architects, engineers and researchers from the hardware design community. There are many different tools for timed Chi that support the analysis and manipulation of timed Chi specifications; and such tools are the results of software engineering research with a very strong foundation in formal theories/methods. Since timed Chi is a well-developed algebraic theory from the field of process algebras with timing, we have the idea that timed Chi is also well-suited for addressing various aspects of hardware systems (discrete-time systems by nature). To show that timed Chi is useful for the formal specification and analysis of hardware systems, we illustrate the use of timed Chi with several benchmark examples of hardware systems

Formal Modeling and Analysis of Timed Systems: Technology Push or Market Pull?

In this short paper I will address the question whether the methods and techniques we develop are applied well in industrial practice. To address this question, I will make a few observations from the academic field, as well as from industrial practice. This will be followed by a concise analysis of the cause of the perceived gap between the academic state-of-the-art and industrial practice. I will conclude with some opportunities for improvement

Simulation and Formal Verification for Improving Safety of PLC Programs

The use of analysis techniques for improving quality of software for industrial controllers is widely used. Mainly Simulation and Formal Verification can be used as complementary techniques improving dependability of mechatronic systems behavior. In this paper there are used Simulation and Formal Verification for guaranteeing safe software for Programmable Logic Controllers, mainly related with using Function blocks of IEC 61131-3 standard. For studying, simulating and verifying behavior of those blocks are used timed automata, as modeling formalism, and UPPAAL, as tool for simulation and Formal Verification purposes

Specification and Analysis of Priced Systems in Priced-Timed Maude

This thesis investigates the suitability of extending the rewriting-logic-based Maude framework, in particular Real-Time Maude, to support the formal modeling and analysis of untimed and timed priced systems. The first contribution of this thesis is to define priced and priced-timed rewrite theories, show the soundness of these definitions, and prove that priced-time rewrite theories contain as a proper subset the set of priced-timed automata (PTA). Since all priced systems that I have encountered have been real-time systems, I focus on priced real-time (priced-timed) systems. The second main contribution of the thesis is the development of a tool, Priced-Timed Maude, supporting the specification and analysis of useful subclasses of priced and priced-timed rewrite theories. In particular, Priced-Timed Maude supports the specification of the large and important class of ``flat'' object-oriented priced-timed systems, for which I have developed useful and intuitive specification techniques. This thesis then applies Priced-Timed Maude to three larger systems, two of which can be considered benchmarks for priced-timed systems and are often encountered in the literature, and one which has been inspired by a ``regular'' problem found in optimization literature. I have also modeled and analyzed one of these systems using the only well known formal tool for priced-timed systems that I have found, the PTA tool Uppaal CORA, and have compared the performance of these Priced-Timed Maude and Uppaal CORA specifications. Unsurprisingly, Uppaal CORA outperforms Priced-Timed Maude when analyzing this problem. This is natural, since the PTA model is quite restrictive. On the other hand, Priced-Timed Maude is more general and expressive, and lets us model more complex systems with advanced data types and communication features in an elegant and intuitive style. Furthermore, Priced-Timed Maude supports a wide range of formal analysis methods, including: rewriting for simulation, search for reachability analysis, linear temporal logic model checking, and finding cost- and time-optimal solutions

Modeling and Analysis of Power-Aware Systems

The paper describes a formal approach for designing and reasoning about power-constrained, timed systems. The framework is based on process algebra, a formalism that has been developed to describe and analyze communicating concurrent systems. The proposed extension allows the modeling of probabilistic resource failures, priorities of resource usages, and power consumption by resources within the same formalism. Thus, it is possible to model alternative power-consumption behaviors and analyze tradeoffs in their timing and other characteristics. This paper describes the modeling and analysis techniques, and illustrates them with examples, including a dynamic voltage-scaling algorithm

Modeling and Analysis of Probabilistic Real-time Systems through Integrating Event-B and Probabilistic Model Checking

Event-B is a formal method used in the development of safety critical systems. However, these systems may introduce uncertainty, and need also to meet real-time requirements, which make their modeling and analysis a challenging task. Existing works on extending Event-B with probability and time did not address both probability and time in a single framework. Besides, they did focus the most on extending the language itself, not on integrating the extended Event-B with verification. In this paper, we aim to represent both probability and time in the Event-B language, and we will show how such a representation can be automatically translated into Probabilistic Timed Automata (PTA) described in the language of the probabilistic model checker PRISM. This translation would allow us to analyze probabilistic, as well as time-bounded probabilistic reachability properties of probabilistic real-time systems through the Probabilistic Timed CTL (PTCTL) logic

Modeling, verification, and analysis of timed actor-based models

In the recent years, formal modeling and verification of realtime systems have become very important. Difficult-to-use modeling languages and inefficient analysis tools are the main obstacles to use formal methods in this domain. Timed actor model is one of the modeling paradigms which is proposed for modeling of realtime systems. It benefits from high-level object-oriented modeling facilities; however, developed analysis techniques for timed actors needs to be improved to make the actor model acceptable for the analysis of real-world applications. In this thesis, we first tackle the model checking problem of timed actors by proposing the standard semantics of timed actors in terms of fine-grained timed transition system (FGTS) and transforming it to Durational Transition Graph (DTG). This way, while the time complexity of model checking algorithms for TCTL properties, in general, is non-polynomial, we are able to check TCTL properties (a subset of TCTL) using model checking in polynomial time. We also improve the model checking algorithm of TCTL properties, obtaining time complexity of O((V lg V+E) |Φ|) instead of O(V(V+E)|Φ|) and use it for efficient model checking of timed actors. In addition, we propose a reduction technique which safely eliminates instantaneous transitions of FGTS. Using the proposed reduction technique, we provide an efficient algorithm for model checking of complete TCTL properties over the reduced transition systems. In actor-based models, the absence of shared variables and the presence of single-threaded actors along with non-preemptive execution of each message server, ensure that the execution of message servers do not interfere with each other. Based on this observation, we propose Floating Time Transition System (FTTS) as the big-step semantics of timed actors. The big-step semantics exploits actor features for relaxing the synchronization of progressof time among actors, and thereby reducing the number of states in transition systems. Considering an actor-based language, we prove there is an action-based weak bisimulation relation between FTTS and FGTS. As a result, the big-step semantics preserves event-based branching-time properties. Finally, we show how Timed Rebeca and FTTS are used as the back-end analysis technique of three different independent works to illustrate the applicability of FTTS in practice.The work on this dissertation was supported by the project “Self-Adaptive Actors:SEADA” (nr. 163205-051) of the Icelandic Research Fund