Problems related to the integration of fault tolerant aircraft electronic systems

Problems related to the design of the hardware for an integrated aircraft electronic system are considered. Taxonomies of concurrent systems are reviewed and a new taxonomy is proposed. An informal methodology intended to identify feasible regions of the taxonomic design space is described. Specific tools are recommended for use in the methodology. Based on the methodology, a preliminary strawman integrated fault tolerant aircraft electronic system is proposed. Next, problems related to the programming and control of inegrated aircraft electronic systems are discussed. Issues of system resource management, including the scheduling and allocation of real time periodic tasks in a multiprocessor environment, are treated in detail. The role of software design in integrated fault tolerant aircraft electronic systems is discussed. Conclusions and recommendations for further work are included

Investigate and classify various types of computer architecture

Issued as Final report, Project no. G-36-60

System on fabrics utilising distributed computing

The main vision of wearable computing is to make electronic systems an important part of everyday clothing in the future which will serve as intelligent personal assistants. Wearable devices have the potential to be wearable computers and not mere input/output devices for the human body. The present thesis focuses on introducing a new wearable computing paradigm, where the processing elements are closely coupled with the sensors that are distributed using Instruction Systolic Array (ISA) architecture. The thesis describes a novel, multiple sensor, multiple processor system architecture prototype based on the Instruction Systolic Array paradigm for distributed computing on fabrics. The thesis introduces new programming model to implement the distributed computer on fabrics. The implementation of the concept has been validated using parallel algorithms. A real-time shape sensing and reconstruction application has been implemented on this architecture and has demonstrated a physical design for a wearable system based on the ISA concept constructed from off-the-shelf microcontrollers and sensors. Results demonstrate that the real time application executes on the prototype ISA implementation thus confirming the viability of the proposed architecture for fabric-resident computing devices

Development of Cluster Computing –A Review

This paper presents the review work of “Cluster Computing” in depth and detail.  Cluster Computing: A Mobile Code Approach by R.B.Patel and Manpreet Singh (2006); Performance Evaluation of Parallel Applications Using Message Passing Interface In Network of Workstations Of Different Computing Powers by Rajkumar Sharma, Priyesh Kanungo and Manohar Chandwani (2011); On the Performance of MPI-OpenMP on a 12 nodes Multi-core Cluster by Abdelgadir Tageldin, Al-Sakib Khan Pathan , Mohiuddin Ahmed (2011); Dynamic Load Balancing in Parallel Processing on Non-Homogeneous Clusters by Armando E. De Giusti, Marcelo R. Naiouf, Laura C. De Giusti, Franco Chichizola (2005); Performance Evaluation of Computation Intensive Tasks in Grid by P.Raghu, K. Sriram (2011); Automatic Distribution of Vision-Tasks on Computing Clusters by Thomas Muller, Binh An Tran and Alois Knoll (2011); Terminology And Taxonomy Parallel Computing Architecture by Amardeep Singh, Satinder Pal Singh, Vandana, Sukhnandan Kaur (2011); Research of Distributed Algorithm based on Parallel Computer Cluster System by Xu He-li, Liu Yan (2010); Cluster Computing Using Orders Based Transparent Parallelizing by Vitaliy D. Pavlenko, Victor V. Burdejnyj (2007) and VCE: A New Personated Virtual Cluster Engine for Cluster Computing by Mohsen Sharifi, Masoud Hassani, Ehsan Mousavi Khaneghah, Seyedeh Leili Mirtaheri (2008). Keywords:Cluster computing, Cluster Architectures, Dynamic and Static Load Balancing, Distributed Systems, Homogeneous and Non-Homogeneous Processors, Multicore clusters, Parallel computing, Parallel Computer Vision, Task parallelism, Terminology and taxonomy, Virtualization, Virtual Cluster

Evaluating local indirect addressing in SIMD proc essors

In the design of parallel computers, there exists a tradeoff between the number and power of individual processors. The single instruction stream, multiple data stream (SIMD) model of parallel computers lies at one extreme of the resulting spectrum. The available hardware resources are devoted to creating the largest possible number of processors, and consequently each individual processor must use the fewest possible resources. Disagreement exists as to whether SIMD processors should be able to generate addresses individually into their local data memory, or all processors should access the same address. The tradeoff is examined between the increased capability and the reduced number of processors that occurs in this single instruction stream, multiple, locally addressed, data (SIMLAD) model. Factors are assembled that affect this design choice, and the SIMLAD model is compared with the bare SIMD and the MIMD models

A characterization of parallel systems

technical reporta taxonomy for parallel processing systems is presented which has some advantages over previous taxonomies. The taxonomy characterizes parallel processing systems using four parameters: topology, communication, granularity, and operation. These parameters and used repetitively in a hierarchical fashion to produce a taxonomic structure which is extensible to the level of detail desired. Topology describes the structure of the priniciple interconnections. Communication describes the flow of data and programs through the system. Granularity describes the size of the largest repeated element, or grain. Operation describes the important functional properties of each grain, especially the ratio of storage to logic circuitry. Granularity and topology are structural parameters, while operation and communication are functional parameters which describe the behavior of the system components. A final section of this paper includes examples of the application of the taxonomy to several parallel processing systems

Deconstructing the Sanders Focus and the Sanders Phase : A Reply to Perttula Regarding the Taxonomy and Significance of the So-called Sanders Focus, or Sanders Phase, Pottery of Northeast Texas and Southeast Oklahoma

Perttula is correct in pointing out that there are numerical errors in a recently published table of mine. A revised version is presented here as Table 1. Although several of these errors are numerically large and might have caused problems had they gone uncorrected, Perttula is not correct in suggesting that they are serious in the sense that they have affected the conclusions I reached based on the table, the insinuation being that they weaken my Sanders entrepot hypothesis. They do not. That hypothesis is part of the reinterpretation of the archeology and bioanthropology of the Arkansas Valley and the Red River Valley which I have been developing for more than eight years. It could hardly be weakened by errors in this table which is simply a compilation of the pottery of the five so-called Sanders focus/phase types reported from the list of sites with probable Sanders phase components recently proffered by Bruseth, Wilson, and Perttula

Improving parallel self-organizing map using heterogeneous uniform memory access / Muhammad Firdaus Mustapha

Self-organizing Map (SOM) is a very popular algorithm that has been used as clustering algorithm and data exploration. SOM consists of complex calculations where the calculation of complexity depending on the circumstances. Many researchers have managed to improve online SOM processing speed using Heterogeneous Computing (HC). HC is a combination of Central Processing Unit (CPU) and Graphic Processing Unit (GPU) that work closely together. Standard HC can be represented by CPU and GPU accessing separate memory blocks. In spite of excellent performance using standard HC, there is a situation that causes computer hardware underutilized when executing online SOM variant. In details, the situation occurs when number of cores is larger than the number of neurons on map. Moreover, the complexities of SOM steps also increase the usage of high memory capacity which leads to high rate memory transfer. This situation is caused by the standard HC implements "deep copies" in storing processing objects which lead to communication latency. Recently, combination CPU and GPU that integrated together on a single chip are rapidly attractive the design paradigm for recent platform because of their remarkable parallel processing abilities. This kind of microprocessor is based on Heterogeneous Unified Memory Access (HUMA) model. This model allows both CPU and GPU to access and store into the same memory location which avoids redundant copies of objects by "deep copies" method. Therefore, the main goal of this research is to reduce computation time of SOM training through implementing on HUMA platform and improve GPU cores utilization. This research has three main objectives to be achieved. Firstly, this research attempts to study the processing natures of original SOM algorithm on standard HC platform. Secondly is to model an enhanced parallel SOM on HUMA-GPU platform and adapting multiple stimuli approach in order to improve the processing speed. Lastly is to evaluate the enhanced parallel SOM in terms of performance accuracy, efficiency, and scalability. This research attempts to improve the processing of SOM algorithm through three stages. The research works start with conducting a preliminary study on sequential SOM algorithm. The research continues to design a parallel SOM architecture based on literature study and implements on two types of architecture; standard HC and HUMA model. Finally, this research designs and implements an enhanced parallel SOM architecture through combining two parallel methods which are network and data partitioning. The combination of the two methods are realized via adapting multiple stimuli approach. This research employs datasets that are acquired from UCI repository. As a result, the enhanced parallel SOM that executed on HUMA platform is able to score up to 1.27 of speed up overall for large map size compared to standard parallel SOM. The proposed work also scores better for smaller map size with scored up to 1.03 of speed up overall compared to standard SOM on the identical platform. Accordingly, the proposed work is able to offer a better solution for small to medium sized of data analysis software. Overall, the solution is enhanced through utilizing recent hardware technology and improved method