An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics

Near-sensor data analytics is a promising direction for IoT endpoints, as it minimizes energy spent on communication and reduces network load - but it also poses security concerns, as valuable data is stored or sent over the network at various stages of the analytics pipeline. Using encryption to protect sensitive data at the boundary of the on-chip analytics engine is a way to address data security issues. To cope with the combined workload of analytics and encryption in a tight power envelope, we propose Fulmine, a System-on-Chip based on a tightly-coupled multi-core cluster augmented with specialized blocks for compute-intensive data processing and encryption functions, supporting software programmability for regular computing tasks. The Fulmine SoC, fabricated in 65nm technology, consumes less than 20mW on average at 0.8V achieving an efficiency of up to 70pJ/B in encryption, 50pJ/px in convolution, or up to 25MIPS/mW in software. As a strong argument for real-life flexible application of our platform, we show experimental results for three secure analytics use cases: secure autonomous aerial surveillance with a state-of-the-art deep CNN consuming 3.16pJ per equivalent RISC op; local CNN-based face detection with secured remote recognition in 5.74pJ/op; and seizure detection with encrypted data collection from EEG within 12.7pJ/op.Comment: 15 pages, 12 figures, accepted for publication to the IEEE Transactions on Circuits and Systems - I: Regular Paper

PhyNetLab: An IoT-Based Warehouse Testbed

Future warehouses will be made of modular embedded entities with communication ability and energy aware operation attached to the traditional materials handling and warehousing objects. This advancement is mainly to fulfill the flexibility and scalability needs of the emerging warehouses. However, it leads to a new layer of complexity during development and evaluation of such systems due to the multidisciplinarity in logistics, embedded systems, and wireless communications. Although each discipline provides theoretical approaches and simulations for these tasks, many issues are often discovered in a real deployment of the full system. In this paper we introduce PhyNetLab as a real scale warehouse testbed made of cyber physical objects (PhyNodes) developed for this type of application. The presented platform provides a possibility to check the industrial requirement of an IoT-based warehouse in addition to the typical wireless sensor networks tests. We describe the hardware and software components of the nodes in addition to the overall structure of the testbed. Finally, we will demonstrate the advantages of the testbed by evaluating the performance of the ETSI compliant radio channel access procedure for an IoT warehouse

Adaptable Security in Wireless Sensor Networks by Using Reconfigurable ECC Hardware Coprocessors

Specific features of Wireless Sensor Networks (WSNs) like the open accessibility to nodes, or the easy observability of radio communications, lead to severe security challenges. The application of traditional security schemes on sensor nodes is limited due to the restricted computation capability, low-power availability, and the inherent low data rate. In order to avoid dependencies on a compromised level of security, a WSN node with a microcontroller and a Field Programmable Gate Array (FPGA) is used along this work to implement a state-of-the art solution based on ECC (Elliptic Curve Cryptography). In this paper it is described how the reconfiguration possibilities of the system can be used to adapt ECC parameters in order to increase or reduce the security level depending on the application scenario or the energy budget. Two setups have been created to compare the software- and hardware-supported approaches. According to the results, the FPGA-based ECC implementation requires three orders of magnitude less energy, compared with a low power microcontroller implementation, even considering the power consumption overhead introduced by the hardware reconfiguratio

Exploiting programmable architectures for WiFi/ZigBee inter-technology cooperation

The increasing complexity of wireless standards has shown that protocols cannot be designed once for all possible deployments, especially when unpredictable and mutating interference situations are present due to the coexistence of heterogeneous technologies. As such, flexibility and (re)programmability of wireless devices is crucial in the emerging scenarios of technology proliferation and unpredictable interference conditions. In this paper, we focus on the possibility to improve coexistence performance of WiFi and ZigBee networks by exploiting novel programmable architectures of wireless devices able to support run-time modifications of medium access operations. Differently from software-defined radio (SDR) platforms, in which every function is programmed from scratch, our programmable architectures are based on a clear decoupling between elementary commands (hard-coded into the devices) and programmable protocol logic (injected into the devices) according to which the commands execution is scheduled. Our contribution is two-fold: first, we designed and implemented a cross-technology time division multiple access (TDMA) scheme devised to provide a global synchronization signal and allocate alternating channel intervals to WiFi and ZigBee programmable nodes; second, we used the OMF control framework to define an interference detection and adaptation strategy that in principle could work in independent and autonomous networks. Experimental results prove the benefits of the envisioned solution

Designing Flexible, Energy Efficient and Secure Wireless Solutions for the Internet of Things

The Internet of Things (IoT) is an emerging concept where ubiquitous physical objects (things) consisting of sensor, transceiver, processing hardware and software are interconnected via the Internet. The information collected by individual IoT nodes is shared among other often heterogeneous devices and over the Internet. This dissertation presents flexible, energy efficient and secure wireless solutions in the IoT application domain. System design and architecture designs are discussed envisioning a near-future world where wireless communication among heterogeneous IoT devices are seamlessly enabled. Firstly, an energy-autonomous wireless communication system for ultra-small, ultra-low power IoT platforms is presented. To achieve orders of magnitude energy efficiency improvement, a comprehensive system-level framework that jointly optimizes various system parameters is developed. A new synchronization protocol and modulation schemes are specified for energy-scarce ultra-small IoT nodes. The dynamic link adaptation is proposed to guarantee the ultra-small node to always operate in the most energy efficiency mode, given an operating scenario. The outcome is a truly energy-optimized wireless communication system to enable various new applications such as implanted smart-dust devices. Secondly, a configurable Software Defined Radio (SDR) baseband processor is designed and shown to be an efficient platform on which to execute several IoT wireless standards. It is a custom SIMD execution model coupled with a scalar unit and several architectural optimizations: streaming registers, variable bitwidth, dedicated ALUs, and an optimized reduction network. Voltage scaling and clock gating are employed to further reduce the power, with a more than a 100% time margin reserved for reliable operation in the near-threshold region. Two upper bound systems are evaluated. A comprehensive power/area estimation indicates that the overhead of realizing SDR flexibility is insignificant. The benefit of baseband SDR is quantified and evaluated. To further augment the benefits of a flexible baseband solution and to address the security issue of IoT connectivity, a light-weight Galois Field (GF) processor is proposed. This processor enables both energy-efficient block coding and symmetric/asymmetric cryptography kernel processing for a wide range of GF sizes (2^m, m = 2, 3, ..., 233) and arbitrary irreducible polynomials. Program directed connections among primitive GF arithmetic units enable dynamically configured parallelism to efficiently perform either four-way SIMD GF operations, including multiplicative inverse, or a long bit-width GF product in a single cycle. This demonstrates the feasibility of a unified architecture to enable error correction coding flexibility and secure wireless communication in the low power IoT domain.PHDComputer Science & EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/137164/1/yajchen_1.pd

TinyVers: A Tiny Versatile System-on-chip with State-Retentive eMRAM for ML Inference at the Extreme Edge

Extreme edge devices or Internet-of-thing nodes require both ultra-low power always-on processing as well as the ability to do on-demand sampling and processing. Moreover, support for IoT applications like voice recognition, machine monitoring, etc., requires the ability to execute a wide range of ML workloads. This brings challenges in hardware design to build flexible processors operating in ultra-low power regime. This paper presents TinyVers, a tiny versatile ultra-low power ML system-on-chip to enable enhanced intelligence at the Extreme Edge. TinyVers exploits dataflow reconfiguration to enable multi-modal support and aggressive on-chip power management for duty-cycling to enable smart sensing applications. The SoC combines a RISC-V host processor, a 17 TOPS/W dataflow reconfigurable ML accelerator, a 1.7 $\mu$W deep sleep wake-up controller, and an eMRAM for boot code and ML parameter retention. The SoC can perform up to 17.6 GOPS while achieving a power consumption range from 1.7 $\mu$W-20 mW. Multiple ML workloads aimed for diverse applications are mapped on the SoC to showcase its flexibility and efficiency. All the models achieve 1-2 TOPS/W of energy efficiency with power consumption below 230 $\mu$W in continuous operation. In a duty-cycling use case for machine monitoring, this power is reduced to below 10 $\mu$W.Comment: Accepted in IEEE Journal of Solid-State Circuit

Anturidatan lähettäminen fyysiseltä kaksoselta digitaaliselle kaksoselle

A digital twin is a digital counterpart of a physical thing such as a machine. The term digital twin was first introduced in 2010. Thereafter, it has received an extensive amount of interest because of the numerous benefits it is expected to offer throughout the product life cycle. Currently, the concept is developed by the world’s largest companies such as Siemens. The purpose of this thesis is to examine which application layer protocols and communication technologies are the most suitable for the sensor data transmission from a physical twin to a digital twin. In addition, a platform enabling this data transmission is developed. As the concept of a digital twin is relatively new, a comprehensive literature view on the definition of a digital twin in scientific literature is presented. It has been found that the vision of a digital twin has evolved from the concepts of ‘intelligent products’ presented at the beginning of the 2000s. The most widely adopted definition states that a digital twin accurately mirrors the current state of its corresponding twin. However, the definition of a digital twin is not yet standardized and varies in different fields. Based on the literature review, the communication needs of a digital twin are derived. Thereafter, the suitability of HTTP, MQTT, CoAP, XMPP, AMQP, DDS, and OPC UA for sensor data transmission are examined through a literature review. In addition, a review of 4G, 5G, NB-IoT, LoRa, Sigfox, Bluetooth, Wi-Fi, Z-Wave, ZigBee, and WirelessHART is presented. A platform for the management of the sensors is developed. The platform narrows the gap between the concept and realization of a digital twin by enabling sensor data transmission. The platform allows easy addition of sensors to a physical twin and provides an interface for their configuration remotely over the Internet. It supports multiple sensor types and application protocols and offers both web user iterface and REST API.Digitaalinen kaksonen on fyysisen tuotteen digitaalinen vastinkappale, joka sisältää tiedon sen nykyisestä tilasta. Digitaalisen kaksosen käsite otettiin ensimmäisen kerran käyttöön vuonna 2010. Sen jälkeen digitaalinen kaksonen on saanut paljon huomiota, ja sitä ovat lähteneet kehittämään maailman suurimmat yritykset, kuten Siemens. Tämän työn tarkoituksena tutkia, mitkä sovelluskerroksen protokollat ja langattomat verkot soveltuvat parhaiten anturien keräämän datan lähettämiseen fyysiseltä kaksoselta digitaaliselle kaksoselle. Sen lisäksi työssä esitellään alusta, joka mahdollistaa tämän tiedonsiirron. Digitaalisen kaksosesta esitetään laaja kirjallisuuskatsaus, joka luo pohjan työn myöhemmille osioille. Digitaalisen kaksosen konsepti pohjautuu 2000-luvun alussa esiteltyihin ajatuksiin ”älykkäistä tuotteista”. Yleisimmän käytössä olevan määritelmän mukaan digitaalinen kaksonen heijastaa sen fyysisen vastinparin tämän hetkistä tilaa. Määritelmä kuitenkin vaihtelee eri alojen välillä eikä se ole vielä vakiintunut tieteellisessä kirjallisuudessa. Kirjallisuuskatsauksen avulla johdetaan digitaalisen kaksosen kommunikaatiotarpeet. Sen jälkeen arvioidaan seuraavien sovelluskerroksen protokollien soveltuvuutta anturidatan lähettämiseen kirjallisuuskatsauksen avulla: HTTP, MQTT, CoAP, XMPP, AMQP, DDS ja OPC UA. Myös seuraavien langattomien verkkojen soveltuvuutta tiedonsiirtoon tutkitaan: 4G, 5G, NB-IoT, LoRaWAN, Sigfox, Bluetooth, Wi-Fi, Z-Wave, ZigBee ja WirelessHART. Osana työtä kehitettiin myös ohjelmistoalusta, joka mahdollistaa anturien hallinnan etänä Internetin välityksellä. Alusta on pieni askel kohti digitaalisen kaksosen käytän-nön toteutusta, sillä se mahdollistaa tiedon keräämisen fyysisestä vastinkappaleesta. Sen avulla sensorien lisääminen fyysiseen kaksoseen on helppoa, ja se tukee sekä useita sensorityyppejä että sovelluskerroksen protokollia. Alusta tukee REST API –rajapintaa ja sisältää web-käyttöliittymän

Design and construction of a novel reconfigurable micro manufacturing cell

This thesis was submitted for the degree of Doctor of Philosophy and awarded by Brunel University.Demands for producing small components are increasing. Such components are usually produced using large-size conventional machining tools. This results in the inadequate usage of resources, including energy, space and time. In the 1990s, the concept of a microfactory was introduced in order to achieve better usage of these resources by scaling down the size of the machine tool itself. Several industries can benefit from implementing such a concept, such as the medical, automotive and electronics industries. A novel architecture for a reconfigurable micro-manufacturing cell (RMC) is presented in this research, aiming at delivering certain manufacturing strategies such as point of use (POU) and cellular manufacturing (CM) as well as several capabilities, including modularity, reconfigurability, mobility and upgradability. Unlike conventional machine tools, the proposed design is capable of providing several machining processes within a small footprint (500 mm2), yet processing parts within a volume up to 100 mm3. In addition, it delivers a rapid structure and process reconfiguration while achieving a micromachining level of accuracy. The approach followed in developing the system is highly iterative with several feedback loops. It was deemed necessary to adopt such an approach to ensure that not only was the design relevant, but also that it progresses the state-of-the-art and takes into account the many considerations in machine design. Following this approach, several design iterations have been developed before reaching a final design that is capable of delivering the required manufacturing qualities and operational performance. A prototype has been built based on the specifications of the selected design iteration, followed by providing a detailed material and components selection process and assembly method before running a performance assessment analysis of the prototype. At this stage, a correlation between the Finite Element Analysis (FEA) model and prototype has been considered, aiming at studying the level of performance of the RMC when optimising the design in the future. Then, based on the data collected during each stage of the design process, an optimisation process was suggested to improve the overall performance of the system, using computer aided design and modelling (CAD/CAM) tools to generate, analyse and optimise the design

Internet of things

This is an introductory course to the IoT (Internet of things). In the early chapters the basics about the IoT are introduced. Then basics of IPv6 internet protocol that is the most used in IoT environment as well as main applications, the current state of the market and the technologies that enable the existence of the IoT are described. Finally the future challenges that are considered most important are discussed.Peer ReviewedPostprint (published version

Ultra-reliable Low-latency, Energy-efficient and Computing-centric Software Data Plane for Network Softwarization

Network softwarization plays a significantly important role in the development and deployment of the latest communication system for 5G and beyond. A more flexible and intelligent network architecture can be enabled to provide support for agile network management, rapid launch of innovative network services with much reduction in Capital Expense (CAPEX) and Operating Expense (OPEX). Despite these benefits, 5G system also raises unprecedented challenges as emerging machine-to-machine and human-to-machine communication use cases require Ultra-Reliable Low Latency Communication (URLLC). According to empirical measurements performed by the author of this dissertation on a practical testbed, State of the Art (STOA) technologies and systems are not able to achieve the one millisecond end-to-end latency requirement of the 5G standard on Commercial Off-The-Shelf (COTS) servers. This dissertation performs a comprehensive introduction to three innovative approaches that can be used to improve different aspects of the current software-driven network data plane. All three approaches are carefully designed, professionally implemented and rigorously evaluated. According to the measurement results, these novel approaches put forward the research in the design and implementation of ultra-reliable low-latency, energy-efficient and computing-first software data plane for 5G communication system and beyond