Ultra thin ultrafine-pitch chip-package interconnections for embedded chip last approach

Ever growing demands for portability and functionality have always governed the electronic technology innovations. IC downscaling with Moore s law and system miniaturization with System-On-Package (SOP) paradigm has resulted and will continue to result in ultraminiaturized systems with unprecedented functionality at reduced cost. The trend towards 3D silicon system integration is expected to downscale IC I/O pad pitches from 40µm to 1- 5 µm in future. Device- to- system board interconnections are typically accomplished today with either wire bonding or solders. Both of these are incremental and run into either electrical or mechanical barriers as they are extended to higher density of interconnections. Alternate interconnection approaches such as compliant interconnects typically require lengthy connections and are therefore limited in terms of electrical properties, although expected to meet the mechanical requirements. As supply currents will increase upto 220 A by 2012, the current density will exceed the maximum allowable current density of solders. The intrinsic delay and electromigration in solders are other daunting issues that become critical at nanometer size technology nodes. In addition, formation of intermetallics is also a bottleneck that poses significant mechanical issues. Recently, many research groups have investigated various techniques for copper-copper direct bonding. Typically, bonding is carried out at 400oC for 30 min followed by annealing for 30 min. High thermal budget in such process makes it less attractive for integrated systems because of the associated process incompatibilities. In the present study, copper-copper bonding at ultra fine-pitch using advanced nano-conductive and non-conductive adhesives is evaluated. The proposed copper-copper based interconnects using advanced conductive and non-conductive adhesives will be a new fundamental and comprehensive paradigm to solve all the four barriers: 1) I/O pitch 2) Electrical performance 3) Reliability and 4) Cost. This thesis investigates the mechanical integrity and reliability of copper-copper bonding using advanced adhesives through test vehicle fabrication and reliability testing. Test vehicles were fabricated using low cost electro-deposition techniques and assembled onto glass carrier. Experimental results show that proposed copper-copper bonding using advanced adhesives could potentially meet all the system performance requirements for the emerging micro/nano-systems.M.S.Committee Chair: Prof. Rao R Tummala; Committee Member: Dr. Jack Moon; Committee Member: Dr. P M Ra

DENSE 3D HETEROGENEOUS INTEGRATION USING SELECTIVE COBALT ALD DEPOSITION AND RECONSTITUTED TIERS

In this thesis, a new fine-pitch low-temperature bonding technology using selective Cobalt (Co) ALD deposition is presented. The benefits of selective Co ALD bonding are nanometer-scale controllability, low planarity requirement, low bonding temperature (200 oC) and potential for ultra-high-density bonds. To demonstrate selective Co ALD bonding, a Cu/Gap/Cu three-layered structure, which emulates 3D ICs stacking, is fabricated and carefully characterized. The testbed shows seamless Co interconnection between the Cu pads after Co ALD deposition for 1000 cycles. The electrical measurements demonstrate over 90% yield, which prove the Co connectivity between the Cu pads. Moreover, in this thesis, a new type of SiO2-reconstituted-tier stacking technology is proposed. The SiO2-reconstituted-tier stacking technology utilizes low-temperature ICP- PECVD SiO2 to encapsulate multi-sized chiplets. After ICP-PECVD SiO2 encapsulation, the through-oxide-vias and the pads are formed on the SiO2 to complete the reconstituted tier before stacking. Compared with conventional epoxy-molding-compound-based stacking, the SiO2 approach can have smaller loss tangent (10x), lower CTE mismatch (3x) and the higher via density (>400x). The thickness of the proposed technology can be over 10 times smaller than conventional epoxy molding. The two technologies, with further analysis and studies, open up exciting new opportunities for future 3D IC heterogeneous integration.M.S

Metal-Alloy Cu Surface Passivation Leads to High Quality Fine-Pitch Bump-Less Cu-Cu Bonding for 3D IC and Heterogeneous Integration Applications

In this paper, we report a low temperature, fine-pitch, bump-less, damascene compatible Cu-Cu thermocompression bonding, using an optimized ultra-thin passivation layer, Constantan, which is an alloy (Copper-Nickel) of 55% Cu and 45% Ni. Surface oxidation and its roughness are the major bottlenecks in achieving high quality, low temperature, and fine-pitch Cu-Cu bonding. In this endeavor, we have used Cu rich alloy (Constantan) for passivation of Cu surface prior to bonding. We have systematically optimized the constantan passivation layer thickness for high quality low temperature, low pressure, bump-less Cu-Cu bonding. Also, we have studied systematically the efficacy of Cu surface passivation with optimized ultra-thin constantan alloy passivation layer. After rigorous trial and optimization, we successfully identified 2 nm passivation layer thickness, at which very high quality Cu-Cu bonding could be accomplished at sub 200 °C with a nominal contact pressure of 0.4 MPa. Post-bonding, electrical and mechanical characterization were validated using four-probe IV measurement and bond strength measurement respectively. Furthermore, Cu-Cu bonding interface was analyzed using IR wafer bonder inspection tool. Very high bond strength of 163 MPa and defect free interface observed by WBI-IR clearly suggests, Cu-Cu finepitch bonding with optimized ultra-thin alloy of 2 nm thick constantan, is of very high quality and reliable. Moreover, this novel bonding approach with alloy based interconnect passivation technique is the prime contestant for future heterogeneous integration

A review of advances in pixel detectors for experiments with high rate and radiation

The Large Hadron Collider (LHC) experiments ATLAS and CMS have established hybrid pixel detectors as the instrument of choice for particle tracking and vertexing in high rate and radiation environments, as they operate close to the LHC interaction points. With the High Luminosity-LHC upgrade now in sight, for which the tracking detectors will be completely replaced, new generations of pixel detectors are being devised. They have to address enormous challenges in terms of data throughput and radiation levels, ionizing and non-ionizing, that harm the sensing and readout parts of pixel detectors alike. Advances in microelectronics and microprocessing technologies now enable large scale detector designs with unprecedented performance in measurement precision (space and time), radiation hard sensors and readout chips, hybridization techniques, lightweight supports, and fully monolithic approaches to meet these challenges. This paper reviews the world-wide effort on these developments.Comment: 84 pages with 46 figures. Review article.For submission to Rep. Prog. Phy

Heterogeneous Integration on Silicon-Interconnect Fabric using fine-pitch interconnects (≤10 �m)

Today, the ever-growing data-bandwidth demand is pushing the boundaries of the traditional printed circuit board (PCB) based integration schemes. Moreover, with the apparent saturation of semiconductor scaling, commonly called Moore's law, system scaling warrants a paradigm shift in packaging technologies, assembly techniques, and integration methodologies. In this work, a superior alternative to PCBs called the Silicon-Interconnect Fabric (Si-IF) is investigated. The Si-IF is a silicon-based, package-less, fine-pitch, highly scalable, heterogeneous integration platform for wafer-scale systems. In this technology, unpackaged dielets are assembled on the Si-IF at small inter-dielet spacings (≤100 �m) using fine-pitch (≤10 �m) die-to-substrate interconnects. A novel assembly process using a solder-less direct metal-metal (gold-gold and copper-copper) thermal compression bonding was developed. Using this process, sub-10 �m pitch interconnects with a low specific contact resistance of ≤0.7 Ω-�m2 were successfully demonstrated. Because of the tightly packed Si-IF assembly, the communication links between the neighboring dies are short (≤500 �m) with low loss (≤2 dB), comparable to on-chip connections. Consequently, simple buffers can transfer data between dies using a Simple Universal Parallel intERface for chips (SuperCHIPS) at low latency (<30 ps), low energy per bit (≤0.03 pJ/b), and high data-rates (up to 10 Gbps/link), corresponding to an aggregate bandwidth up to 8 Tbps/mm. The benefits of the SuperCHIPS protocol were experimentally demonstrated to provide 5-90X higher data-bandwidth, 8-30X lower latency, and 5-40X lower energy per bit compared to existing integration schemes. This dissertation addresses the assembly technology and communication protocols of the Si-IF technology

異種ダイレット積層を用いたフレキシブルハイブリッドデバイスの集積技術に関する研究

Tohoku University福島誉史課

Investigation of Cu‑Cu bonding for 2.5D and 3D system integration using self‑assembled monolayer as oxidation inhibitor

Das Cu-Cu-Bonden ist eine vielversprechende lötfreie Fine-Pitch-Verbindungstechnologie für die 2,5D- und 3D-Systemintegration. Diese Bondtechnologie wurde in den letzten Jahren intensiv untersucht und wird derzeit für miniaturisierte mikroelektronische Produkte eingesetzt. Allerdings, stellt das Cu‑Cu-Bonden zum einen sehr hohe Anforderungen an die Oberflächenplanarität und -reinheit, und zum anderen sollten die Bondpartner frei von Oxiden sein. Oxidiertes Cu erfordert erhöhte Bondparameter, um die Oxidschicht zu durchbrechen und zuverlässige Cu-Cu-Verbindungen zu erzielen. Diese Bondbedingungen sind für viele sensible Bauelemente nicht geeignet. Aus diesem Grund sollten alternative Technologien mit einer einfachen Technik zum Schutz von Cu vor Oxidation gefunden werden. In dieser Arbeit werden selbstorganisierte Monolagen (SAMs) für den Cu-Oxidationsschutz und die Verbesserung der Cu-Cu-Thermokompression- (TC) und Ultraschall- (US) Flip-Chip-Bondtechnologien untersucht. Die Experimente werden an Si-Chips mit galvanisch aufgebrachten Cu-Microbumps und Cu-Schichten durchgeführt. Die Arbeit beinhaltet die umfassende Charakterisierung der SAM für den Cu-Schutz, die Bewertung der technologischen Parameter für das TC- und US-Flip-Chip-Bonden sowie die Charakterisierung der Cu-Cu-Bondqualität (Scherfestigkeitstests, Bruchflächen- und Mikrostrukturanalysen). Eine Lagerung bei tiefen Temperaturen (bei ‑18 °C und ‑40 °C) bestätigte die langanhaltende Schutzwirkung der kurzkettigen SAMs für das galvanisch abgeschiedene Cu ohne chemisch-mechanische Politur. Der Einfluss der Tieftemperaturlagerung an Luft und der thermischen SAM-Desorption in einer Inertgasatmosphäre auf die TC-Verbindungsqualität wird im Detail analysiert. Die Idee, mit Hilfe der US-Leistung SAM mechanisch zu entfernen und gleichzeitig das US-Flip-Chip-Bonden zu starten, wurde in der Literatur bisher nicht systematisch untersucht. Die Methode ermöglicht kurze Bondzeiten, niedrige Bondtemperaturen und das Bonden an Umgebungsluft. Sowohl beim TC- als auch beim US-Flip-Chip-Bonden zeigt es sich, dass die Scherfestigkeit bei den Proben mit SAM-Passivierung um ca. 30 % höher ist als bei unbeschichteten Proben. Das Vorhandensein von Si- und Ti-Bruchflächen nach den Scherfestigkeitstests ist für die Proben mit der SAM-Passivierung typisch, was auf eine höhere Festigkeit solcher Verbindungen im Vergleich zu ungeschützten Proben schließen lässt. Die Transmissionselektronenmikroskopie (TEM) zeigt keine SAM-Spuren im zentralen Bereich der Cu-Cu-Grenzfläche nach dem US-Flip-Chip-Bonden. Die Ergebnisse dieser Arbeit zeigen die Verbesserung der Bondqualität durch den Einsatz von SAM zum Schutz des Cu vor Oxidation im Vergleich zum üblicherweise angewandten Cu-Vorätzen. Das gefundene technologische Prozessfenster für das US-Flip-Chip-Bonden an Luft bietet eine hohe Bondqualität bei 90 °C und 150 °C, bei 180 MPa, bei einer Bonddauer von 1 s an. Die in dieser Arbeit gewonnenen Erkenntnisse sind ein wichtiger Beitrag zum Verständnis des SAM-Einflusses auf Chips mit galvanischen Cu-Microbumps, bzw. Cu-Schichten, und zur weiteren Anwendung der Cu-Cu-Fine-Pitch-Bondtechnologie in der Mikroelektronik.Cu-Cu bonding is one of the most promising fine-pitch interconnect technologies with solder elimination for 2.5D and 3D system integration. This bonding technology has been intensively investigated in the last years and is currently in application for miniaturized microelectronics products. However, Cu-Cu bonding has very high demands on the sur-face planarity and purity, and the bonding partners should be oxide-free. Oxidized Cu requires elevated bonding parameters in order to break through the oxide layer and achieve reliable Cu-Cu interconnects. Those bonding conditions are undesirable for many devices (e.g. due to the temperature/pressure sensitivity). Therefore, alternative technologies with a simple technique for Cu protection from oxidation are required. Self-assembled monolayers (SAMs) are proposed for the Cu protection and the improvement of the Cu-Cu thermocompression (TC) and ultrasonic (US) flip-chip bonding technologies in this thesis. The experiments were carried out on Si dies with electroplated Cu microbumps and Cu layers. The thesis comprises the comprehensive characterization of the SAM for Cu protection, evaluation of technological parameters for TC and US flip-chip bonding as well as characterization of the Cu-Cu bonding quality (shear strength tests, fracture surface and microstructure analyses). The storage at low temperatures (at ‑18 °C and ‑40 °C) confirmed the prolonged protective effect of the short-chain SAMs for the electroplated Cu without chemical-mechanical polishing. The influence of the low-temperature storage in air and the thermal SAM desorption in an inert gas atmosphere on the TC bonding quality was analyzed in detail. The approach of using US power to mechanically remove SAM and simultaneously start the US flip-chip bonding has not been systematically investigated before. The method provides the benefit of short bonding time, low bonding temperature and bonding in ambient air. Both the TC and US flip-chip bonding results featured the shear strength that is approximately 30 % higher for the samples with SAM passivation in comparison to the uncoated samples. The presence of Si and Ti fracture surfaces after the shear strength tests is typical for the samples with the SAM passivation, which suggests a higher strength of such interconnects in comparison to the uncoated samples. The transmission electron microscopy (TEM) indicated no SAM traces at the central region of the Cu-Cu bonding interface after the US flip-chip bonding. The results of this thesis show the improvement of the bonding quality caused by the application of SAM for Cu protection from oxidation in comparison to the commonly applied Cu pre-treatments. The found technological process window for the US flip-chip bonding in air offers high bonding quality at 90 °C and 150 °C, at 180 MPa, for the bonding duration of 1 s. The knowledge gained in this thesis is an important contribution to the understanding of the SAM performance on chips with electroplated Cu microbumps/layers and further application of the Cu-Cu fine-pitch bonding technology for microelectronic devices

Nanowires for 3d silicon interconnection – low temperature compliant nanowire-polymer film for z-axis interconnect

Semiconductor chip packaging has evolved from single chip packaging to 3D heterogeneous system integration using multichip stacking in a single module. One of the key challenges in 3D integration is the high density interconnects that need to be formed between the chips with through-silicon-vias (TSVs) and inter-chip interconnects. Anisotropic Conductive Film (ACF) technology is one of the low-temperature, fine-pitch interconnect method, which has been considered as a potential replacement for solder interconnects in line with continuous scaling of the interconnects in the IC industry. However, the conventional ACF materials are facing challenges to accommodate the reduced pad and pitch size due to the micro-size particles and the particle agglomeration issue. A new interconnect material - Nanowire Anisotropic Conductive Film (NW-ACF), composed of high density copper nanowires of ~ 200 nm diameter and 10-30 µm length that are vertically distributed in a polymeric template, is developed in this work to tackle the constrains of the conventional ACFs and serves as an inter-chip interconnect solution for potential three-dimensional (3D) applications

Study of the impact of lithography techniques and the current fabrication processes on the design rules of tridimensional fabrication technologies

Working for the photolithography tool manufacturer leader sometimes gives me the impression of how complex and specific is the sector I am working on. This master thesis topic came with the goal of getting the overall picture of the state-of-the-art: stepping out and trying to get a helicopter view usually helps to understand where a process is in the productive chain, or what other firms and markets are doing to continue improvingUniversidad de sevilla.Máster Universitario en Microelectrónica: Diseño y Aplicaciones de Sistemas Micro/Nanométrico

High-Density Solid-State Memory Devices and Technologies

This Special Issue aims to examine high-density solid-state memory devices and technologies from various standpoints in an attempt to foster their continuous success in the future. Considering that broadening of the range of applications will likely offer different types of solid-state memories their chance in the spotlight, the Special Issue is not focused on a specific storage solution but rather embraces all the most relevant solid-state memory devices and technologies currently on stage. Even the subjects dealt with in this Special Issue are widespread, ranging from process and design issues/innovations to the experimental and theoretical analysis of the operation and from the performance and reliability of memory devices and arrays to the exploitation of solid-state memories to pursue new computing paradigms