Peptide mass fingerprinting using field-programmable gate arrays

The reconfigurable computing paradigm, which exploits the flexibility and versatility of field-programmable gate arrays (FPGAs), has emerged as a powerful solution for speeding up time-critical algorithms. This paper describes a reconfigurable computing solution for processing raw mass spectrometric data generated by MALDI-TOF instruments. The hardware-implemented algorithms for denoising, baseline correction, peak identification, and deisotoping, running on a Xilinx Virtex-2 FPGA at 180 MHz, generate a mass fingerprint that is over 100 times faster than an equivalent algorithm written in C, running on a Dual 3-GHz Xeon server. The results obtained using the FPGA implementation are virtually identical to those generated by a commercial software package MassLynx

Empowering parallel computing with field programmable gate arrays

After more than 30 years, reconfigurable computing has grown from a concept to a mature field of science and technology. The cornerstone of this evolution is the field programmable gate array, a building block enabling the configuration of a custom hardware architecture. The departure from static von Neumannlike architectures opens the way to eliminate the instruction overhead and to optimize the execution speed and power consumption. FPGAs now live in a growing ecosystem of development tools, enabling software programmers to map algorithms directly onto hardware. Applications abound in many directions, including data centers, IoT, AI, image processing and space exploration. The increasing success of FPGAs is largely due to an improved toolchain with solid high-level synthesis support as well as a better integration with processor and memory systems. On the other hand, long compile times and complex design exploration remain areas for improvement. In this paper we address the evolution of FPGAs towards advanced multi-functional accelerators, discuss different programming models and their HLS language implementations, as well as high-performance tuning of FPGAs integrated into a heterogeneous platform. We pinpoint fallacies and pitfalls, and identify opportunities for language enhancements and architectural refinements

Image processing applications using a novel parallel computing machine based on reconfigurable logic

Zelig is a 32 physical node fine-grained computer employing field-programmable gate arrays. Its application to the high speed implementation of various image pre-processing operations (in particular binary morphology) is described together with typical speed-up result

Field Programmable Gate Arrays (FPGAs) II

This Edited Volume Field Programmable Gate Arrays (FPGAs) II is a collection of reviewed and relevant research chapters, offering a comprehensive overview of recent developments in the field of Computer and Information Science. The book comprises single chapters authored by various researchers and edited by an expert active in the Computer and Information Science research area. All chapters are complete in itself but united under a common research study topic. This publication aims at providing a thorough overview of the latest research efforts by international authors on Computer and Information Science, and open new possible research paths for further novel developments

Inverted spin polarization of Heusler alloys for new spintronic devices

A new magnetic logic overcomes the major limitations of field programmable gate arrays while having a 50% smaller unit cell than conventional designs utilizing magnetic tunnel junctions with one Heusler alloy electrode. These show positive and negative TMR values at different bias voltages at room temperature which generally adds an additional degree of freedom to all spintronic devices

Method for Testing Field Programmable Gate Arrays

A method of testing field programmable gate arrays (FPGAs) includes the step of configuring programmable logic blocks of the FPGAs for completing a built-in self-test. Specifically, the FPGA under test may be configured to act as an iterative logic array wherein a first group of programmable logic blocks are configured as test pattern generators, output response analyzers and helper cells, and a second group of programmable logic blocks are configured as blocks under test. The blocks under test are then repeatedly reconfigured in order to completely test each block under test in all possible modes of operation. The first and second groups of programmable logic blocks are then repeatedly rearranged so that all the programmable logic blocks are established as blocks under test at least once. Following the rearrangement, the repeated reconfiguration of the blocks under test is performed once again

Method for Testing Field Programmable Gate Arrays

A method of testing field programmable gate arrays (FPGAs) includes the step of configuring programmable logic blocks of the FPGAs for completing a built-in self-test. This is followed by the steps of initiating the built-in self-test, generating test patterns with the programmable logic blocks and analyzing a resulting response to produce a pass/fail indication with the programmable logic blocks. More specifically, the configuring step includes establishing a first group of programmable logic blocks as test pattern generators and output response analyzers and a second group of programmable logic blocks as blocks under test. The blocks under test are then repeatedly recongifured in order to completely test each block under test in all possible modes of operation. The programming of the first and second groups of programmable logic blocks is then reversed and the testing of each new block under test is then completed

Digital Fingerprinting of Field Programmable Gate Arrays

Commercial off-the-shelf (COTS) component usage is becoming more prevalent in military applications due to current Department of Defense (DoD) policies. The easy accessibility of COTS will give reverse engineers a higher probability of successfully tampering, coping, or reverse engineering circuits that contain critical capabilities. To prevent this and verify the trustworthiness of hardware, circuit identification tags or serials numbers can be used. However, these values can be easily obtained and forged. To protect critical DoD technologies from possible exploitation, there is an urgent need for a reliable method to confirm a circuit’s identity using a set of unique unforgettable metrics. This research proposes the concept of creating a circuit identifier, or digital fingerprint, for application specific integrated circuits (ASIC) and field programmable gate arrays (FPGAs). The digital fingerprint would be a function of the natural variations in the semiconductor manufacturing process and the functionality of the circuit allowing the creation of a unique identifier for a specific chip that can not be duplicated or forged. The proposed digital fingerprint allows the use of any arbitrary node or set of nodes internal to the circuit and the circuit outputs as monitoring locations. Changes in the signal on a selected node or output can be quantified digitally over a period of time or at a specific instance of time. Two monitoring methods are proposed, one using cumulative observation of the nodes and the other samples the nodes based on a signal transition. Testing of the two monitoring methods was performed on a small sample of twenty Xilinx® Virtex-II Pro FPGAs. Both methods successfully created unique identifiers for each FPGA

A user-friendly fully digital TDPAC-spectrometer

A user-friendly fully digital TDPAC-spectrometer with six detectors and fast digitizers using Field Programmable Gate Arrays is described and performance data are given