Graph model analysis of computer structures

Graph theory is applicable to the solving of problems in nearly every field of scientific study. The purpose of this thesis is to consider its applications in representing and analyzing digital computers. Fundamental graph theory definitions, the types and the properties of the directed graphs, the matrix representation, and several reduction techniques are discussed. The blocking gate method for diagnosing computer systems is described and applied to the Scientific Control Corporation (SCC) 650 for its fault-diagnosis. Microprogramming has been a significant trend in hardware and software designs of computers. Microprogrammed computers are discussed in comparison to conventional computers. A general scheme utilizing four nodes generates directed graphs for both types of architecture. The directed graphs are studied with respect to the flexibility and cost parameters --Abstract, page ii

A microprogrammed control path architecture for an embedded IEEE 1149.1 test coprocessor

This paper proposes a test coprocessor for a 32-bitMicroBlaze CPU core. A microprogrammed architecture is usedto implement the coprocessor control path, offering a flexiblesolution that ensures a straightforward expansion of the testcommand set. The current version supports a set of SVF-likecommands that is able to control one built-in IEEE 1149.1boundary-scan infrastructure. The proposed test coprocessor isuseful in a wide range of online test applications, and namely inthe case of mission-critical embedded systems, where online faultdetection and diagnosis become particularly important

Design of a Microprogram Control Unit with Concurrent Error Detection

Coordinated Science Laboratory was formerly known as Control Systems LaboratoryOffice of Naval Research / N00039-80-C-0556U of I OnlyRestricted to UIUC communit

Measurement of SIFT operating system overhead

The overhead of the software implemented fault tolerance (SIFT) operating system was measured. Several versions of the operating system evolved. Each version represents different strategies employed to improve the measured performance. Three of these versions are analyzed. The internal data structures of the operating systems are discussed. The overhead of the SIFT operating system was found to be of two types: vote overhead and executive task overhead. Both types of overhead were found to be significant in all versions of the system. Improvements substantially reduced this overhead; even with these improvements, the operating system consumed well over 50% of the available processing time

A high level disc controller

Includes bibliographical references.Since the emergence of the digital computer in the 1940s, computer architecture has been largely dictated by the requirements of mathematicians and scientists. Trends have thus been towards processing data as quickly and as accurately as possible. Even now, in the age of large scale integration culminating in the microprocessor, internal structures remain committed to these ideals. This is not surprising since the main users of computers are involved with data processing and scientific computing. The process control engineer, who turned to the digital computer to provide the support he required in his ever increasing strive towards automation, has had therefore to use these generalized computing structures. His basic requirements however, are somewhat different to those of the data processing manager or the scientific user. He has to contend with an inherent problem of synchronizing the computer to the real-world timing of his plants. He is far more interested in the response time of the computer to an external occurrence than he is to sheer 'number-crunching' power. Despite the trends in process control towards distributed computing, even the most advanced systems require a relatively large central processor. This processor is called upon to carry out a wide variety of different tasks most of which are 'requested' by external events. Multiprogramming facilities are therefore essential and are normally effected by means of a real-time operating system. One of the prime objectives of such a real time operating system is to permit the various programs to be run at the required time on some priority basis. In many cases these routines can be large - thus requiring access to backing storage. Traditionally the backing store, implemented by a moving-head disc for example is under the control of the real-time operating system. This can have serious consequences. If real-time requirements are to be met, transfer to and from the disc must be made as rapidly as possible. Also, in initiating and controlling such transfer, the computer is using time which otherwise could be avai1ab1e for useful, process-orientated work. With the rapid advancement of digital technology, the time is c1ear1y right to examine our present computer architecture. This dissertation explores the problem area previously discussed - the control over the bulk storage device in a real-time process-control computer system. It is proposed that a possible solution lies in the development of an intelligent backing-store controller. This essentially combines the conventional low-level backing store interface with a special purpose processor which handles all file routines. This dissertation demonstrates how such a structure can be implemented using current technology, and will evaluate its inherent advantages

Design of a modular digital computer system, CDRL no. D001, final design plan

The engineering breadboard implementation for the CDRL no. D001 modular digital computer system developed during design of the logic system was documented. This effort followed the architecture study completed and documented previously, and was intended to verify the concepts of a fault tolerant, automatically reconfigurable, modular version of the computer system conceived during the architecture study. The system has a microprogrammed 32 bit word length, general register architecture and an instruction set consisting of a subset of the IBM System 360 instruction set plus additional fault tolerance firmware. The following areas were covered: breadboard packaging, central control element, central processing element, memory, input/output processor, and maintenance/status panel and electronics