Fractional strong matching preclusion for two variants of hypercubes

Let F be a subset of edges and vertices of a graph G. If G-F has no fractional perfect matching, then F is a fractional strong matching preclusion set of G. The fractional strong matching preclusion number is the cardinality of a minimum fractional strong matching preclusion set. In this paper, we mainly study the fractional strong matching preclusion problem for two variants of hypercubes, the multiply twisted cube and the locally twisted cube, which are two of the most popular interconnection networks. In addition, we classify all the optimal fractional strong matching preclusion set of each

Interconnection Networks Embeddings and Efficient Parallel Computations.

To obtain a greater performance, many processors are allowed to cooperate to solve a single problem. These processors communicate via an interconnection network or a bus. The most essential function of the underlying interconnection network is the efficient interchanging of messages between processes in different processors. Parallel machines based on the hypercube topology have gained a great respect in parallel computation because of its many attractive properties. Many versions of the hypercube have been introduced by many researchers mainly to enhance communications. The twisted hypercube is one of the most attractive versions of the hypercube. It preserves the important features of the hypercube and reduces its diameter by a factor of two. This dissertation investigates relations and transformations between various interconnection networks and the twisted hypercube and explore its efficiency in parallel computation. The capability of the twisted hypercube to simulate complete binary trees, complete quad trees, and rings is demonstrated and compared with the hypercube. Finally, the fault-tolerance of the twisted hypercube is investigated. We present optimal algorithms to simulate rings in a faulty twisted hypercube environment and compare that with the hypercube

Processor allocation strategies for modified hypercubes

Parallel processing has been widely accepted to be the future in high speed computing. Among the various parallel architectures proposed/implemented, the hypercube has shown a lot of promise because of its poweful properties, like regular topology, fault tolerance, low diameter, simple routing, and ability to efficiently emulate other architectures. The major drawback of the hypercube network is that it can not be expanded in practice because the number of communication ports for each processor grows as the logarithm of the total number of processors in the system. Therefore, once a hypercube supercomputer of a certain dimensionality has been built, any future expansions can be accomplished only by replacing the VLSI chips. This is an undesirable feature and a lot of work has been under progress to eliminate this stymie, thus providing a platform for easier expansion. Modified hypercubes (MHs) have been proposed as the building blocks of hypercube-based systems supporting incremental growth techniques without introducing extra resources for individual hypercubes. However, processor allocation on MHs proves to be a challenge due to a slight deviation in their topology from that of the standard hypercube network. This thesis addresses the issue of processor allocation on MHs and proposes various strategies which are based, partially or entirely, on table look-up approaches. A study of the various task allocation strategies for standard hypercubes is conducted and their suitability for MHs is evaluated. It is shown that the proposed strategies have a perfect subcube recognition ability and a superior performance. Existing processor allocation strategies for pure hypercube networks are demonstrated to be ineffective for MHs, in the light of their inability to recognize all available subcubes. A comparative analysis that involves the buddy strategy and the new strategies is carried out using simulation results

Parallel Computation on Hypercube-Like Machines.

The hypercube interconnection network has been recognized to be very suitable for a parallel computing architecture due to its attractive topological properties. Recently, several modified hypercubes have been propose to improve the performance of a hypercube. This dissertation deals with two modified hypercubes, the X-hypercube and the Z-cube. The X-hypercube is a variant of the hypercube, with the same amount of hardware but a diameter of only $\lceil$(n + 1)/2$\rceil$ in a hypercube of dimension n. The Z-cube has only 75 percent of the edges of a hypercube with the same number vertices and the same diameter as the hypercube. In this dissertation, we investigate some topological properties and the effectiveness of the X-hypercube and the Z-cube in their combinatorial and computational aspects. We give the optimal or nearly optimal data communication algorithms including routing, broadcasting, and census function for the X-hypercube and the Z-cube. We also give the optimal embedding algorithms between the X-hypercube and the hypercube. It is shown that the average distance between vertices in a X-hypercube is roughly 13/16 of that in a hypercube. This implies that a X-hypercube achieves the better average communication performance than a hypercube. In addition, a set of fundamental SIMD algorithms for a X-hypercube is given. Our results indicate that the X-hypercube makes an improvement in performance over the hypercube, but not as much as the reduction in a diameter, and the Z-cube is a good alternative for the hypercube as far as the VLSI implementation is of major concern

ONE BY ONE EMBEDDING THE CROSSED HYPERCUBE INTO PANCAKE GRAPH

Let G and H be two simple undirected graphs. An embedding of the graph G into the graph H is an injective mapping f from vertices of G to the vertices of H. The dilation of embedding is the maximum distance between f(u), f(v) taken over edges (u, v) of G. The Pancake graph is one as viable interconnection scheme for parallel computers, which has been examined by a number of researchers. The Pancake was proposed as alternatives to the hypercube for interconnecting processors in parallel computer. Some good attractive properties of this interconnection network include: vertex symmetry, small degree, a sub-logarithmic diameter, extendability, and high connectivity (robustness), easy routing and regularity of topology, fault tolerance, extensibility and embeddability of others topologies. In this paper, we give a construction of one by one embedding of dilation 5 of crossed hypercube into Pancake graph

System data communication structures for active-control transport aircraft, volume 2

The application of communication structures to advanced transport aircraft are addressed. First, a set of avionic functional requirements is established, and a baseline set of avionics equipment is defined that will meet the requirements. Three alternative configurations for this equipment are then identified that represent the evolution toward more dispersed systems. Candidate communication structures are proposed for each system configuration, and these are compared using trade off analyses; these analyses emphasize reliability but also address complexity. Multiplex buses are recognized as the likely near term choice with mesh networks being desirable for advanced, highly dispersed systems

Automorphisms generating disjoint Hamilton cycles in star graphs

In the first part of the thesis we define an automorphism φn for each star graph Stn of degree n − 1, which yields permutations of labels for the edges of Stn taken from the set of integers {1, . . . , bn/2c}. By decomposing these permutations into permutation cycles, we are able to identify edge-disjoint Hamilton cycles that are automorphic images of a known two-labelled Hamilton cycle H1 2(n) in Stn. Our main result is an improvement from the existing lower bound of bϕ(n)/10c to b2ϕ(n)/9c, where ϕ is Euler’s totient function, for the known number of edge-disjoint Hamilton cycles in Stn for all odd integers n. For prime n, the improvement is from bn/8c to bn/5c. We extend this result to the cases when n is the power of a prime other than 3 and 7. The second part of the thesis studies ‘symmetric’ collections of edge-disjoint Hamilton cycles in Stn, i.e. collections that comprise images of H1 2(n) under general label-mapping automorphisms. We show that, for all even n, there exists a symmetric collection of bϕ(n)/2c edge-disjoint Hamilton cycles, and Stn cannot have symmetric collections of greater than bϕ(n)/2c such cycles for any n. Thus, Stn is not symmetrically Hamilton decomposable if n is not prime. We also give cases of even n, in terms of Carmichael’s reduced totient function λ, for which ‘strongly’ symmetric collections of edge-disjoint Hamilton cycles, which are generated from H1 2(n) by a single automorphism, can and cannot attain the optimum bound bϕ(n)/2c for symmetric collections. In particular, we show that if n is a power of 2, then Stn has a spanning subgraph with more than half of the edges of Stn, which is strongly symmetrically Hamilton decomposable. For odd n, it remains an open problem as to whether the bϕ(n)/2c can be achieved for symmetric collections, but we are able to show that, for certain odd n, a ϕ(n)/4 bound is achievable and optimal for strongly symmetric collections. The search for edge-disjoint Hamilton cycles in star graphs is important for the design of interconnection network topologies in computer science. All our results improve on the known bounds for numbers of any kind of edge-disjoint Hamilton cycles in star graphs

The connection machine

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1988.Bibliography: leaves 134-157.by William Daniel Hillis.Ph.D

The Fifth NASA Symposium on VLSI Design

The fifth annual NASA Symposium on VLSI Design had 13 sessions including Radiation Effects, Architectures, Mixed Signal, Design Techniques, Fault Testing, Synthesis, Signal Processing, and other Featured Presentations. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The presentations share insights into next generation advances that will serve as a basis for future VLSI design