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Fast, non-monte-carlo estimation of transient performance variation due to device mismatch
This paper describes an efficient way of simulating the effects of device random mismatch on circuit transient characteristics, such as variations in delay or in frequency. The proposed method models DC random offsets as equivalent AC pseudo-noises and leverages the fast, linear periodically time-varying (LPTV) noise analysis available from RF circuit simulators. Therefore, the method can be considered as an extension to DC match analysis and offers a large speed-up compared to the traditional Monte-Carlo analysis. Although the assumed linear perturbation model is valid only for small variations, it enables easy ways to estimate correlations among variations and identify the most sensitive design parameters to mismatch, all at no additional simulation cost. Three benchmarks measuring the variations in the input offset voltage of a clocked comparator, the delay of a logic path, and the frequency of an oscillator demonstrate the speed improvement of about 100-1000x compared to a 1000-point Monte-Carlo method
System level performance and yield optimisation for analogue integrated circuits
Advances in silicon technology over the last decade have led to increased integration of analogue and digital functional blocks onto the same single chip. In such a mixed signal environment, the analogue circuits must use the same process technology as their digital neighbours. With reducing transistor sizes, the impact of process variations on analogue design has become prominent and can lead to circuit performance falling below specification and hence reducing the yield.This thesis explores the methodology and algorithms for an analogue integrated circuit automation tool that optimizes performance and yield. The trade-offs between performance and yield are analysed using a combination of an evolutionary algorithm and Monte Carlo simulation. Through the integration of yield parameter into the optimisation process, the trade off between the performance functions can be better treated that able to produce a higher yield. The results obtained from the performance and variation exploration are modelled behaviourally using a Verilog-A language. The model has been verified with transistor level simulation and a silicon prototype.For a large analogue system, the circuit is commonly broken down into its constituent sub-blocks, a process known as hierarchical design. The use of hierarchical-based design and optimisation simplifies the design task and accelerates the design flow by encouraging design reuse.A new approach for system level yield optimisation using a hierarchical-based design is proposed and developed. The approach combines Multi-Objective Bottom Up (MUBU) modelling technique to model the circuit performance and variation and Top Down Constraint Design (TDCD) technique for the complete system level design. The proposed method has been used to design a 7th order low pass filter and a charge pump phase locked loop system. The results have been verified with transistor level simulations and suggest that an accurate system level performance and yield prediction can be achieved with the proposed methodology
Power quality and electromagnetic compatibility: special report, session 2
The scope of Session 2 (S2) has been defined as follows by the Session Advisory Group and the Technical Committee: Power Quality (PQ), with the more general concept of electromagnetic compatibility (EMC) and with some related safety problems in electricity distribution systems.
Special focus is put on voltage continuity (supply reliability, problem of outages) and voltage quality (voltage level, flicker, unbalance, harmonics). This session will also look at electromagnetic compatibility (mains frequency to 150 kHz), electromagnetic interferences and electric and magnetic fields issues. Also addressed in this session are electrical safety and immunity concerns (lightning issues, step, touch and transferred voltages).
The aim of this special report is to present a synthesis of the present concerns in PQ&EMC, based on all selected papers of session 2 and related papers from other sessions, (152 papers in total). The report is divided in the following 4 blocks:
Block 1: Electric and Magnetic Fields, EMC, Earthing systems
Block 2: Harmonics
Block 3: Voltage Variation
Block 4: Power Quality Monitoring
Two Round Tables will be organised:
- Power quality and EMC in the Future Grid (CIGRE/CIRED WG C4.24, RT 13)
- Reliability Benchmarking - why we should do it? What should be done in future? (RT 15
Contributions on using embedded memory circuits as physically unclonable functions considering reliability issues
[eng] Moving towards Internet-of-Things (IoT) era, hardware security becomes a crucial
research topic, because of the growing demand of electronic products that are remotely
connected through networks. Novel hardware security primitives based on
manufacturing process variability are proposed to enhance the security of the IoT
systems. As a trusted root that provides physical randomness, a physically unclonable
function is an essential base for hardware security.
SRAM devices are becoming one of the most promising alternatives for the
implementation of embedded physical unclonable functions as the start-up value of
each bit-cell depends largely on the variability related with the manufacturing process.
Not all bit-cells experience the same degree of variability, so it is possible that some cells
randomly modify their logical starting value, while others will start-up always at the
same value. However, physically unclonable function applications, such as identification
and key generation, require more constant logical starting value to assure high reliability
in PUF response. For this reason, some kind of post-processing is needed to correct the
errors in the PUF response.
Unfortunately, those cells that have more constant logic output are difficult to be
detected in advance. This work characterizes by simulation the start-up value
reproducibility proposing several metrics suitable for reliability estimation during design
phases. The aim is to be able to predict by simulation the percentage of cells that will be
suitable to be used as PUF generators. We evaluate the metrics results and analyze the
start-up values reproducibility considering different external perturbation sources like several power supply ramp up times, previous internal values in the bit-cell, and
different temperature scenarios. The characterization metrics can be exploited to
estimate the number of suitable SRAM cells for use in PUF implementations that can be
expected from a specific SRAM design.[cat] En lâera de la Internet de les coses (IoT), garantir la seguretat del hardware ha
esdevingut un tema de recerca crucial, en especial a causa de la creixent demanda de
productes electrĂČnics que es connecten remotament a travĂ©s de xarxes. Per millorar la
seguretat dels sistemes IoT, sâhan proposat noves solucions hardware basades en la
variabilitat dels processos de fabricaciĂł. Les funcions fĂsicament inclonables (PUF)
constitueixen una font fiable dâaleatorietat fĂsica i sĂłn una base essencial per a la
seguretat hardware.
Les memĂČries SRAM sâestan convertint en una de les alternatives mĂ©s prometedores per
a la implementaciĂł de funcions fĂsicament inclonables encastades. AixĂČ Ă©s aixĂ ja que el
valor dâencesa de cada una de les cel·les que formen els bits de la memĂČria depĂšn en
gran mesura de la variabilitat prĂČpia del procĂ©s de fabricaciĂł. No tots els bits tenen el
mateix grau de variabilitat, aixĂ que algunes cel·les canvien el seu estat lĂČgic dâencesa de
forma aleatĂČria entre enceses, mentre que dâaltres sempre assoleixen el mateix valor
en totes les enceses. No obstant aixĂČ, les funcions fĂsicament inclonables, que sâutilitzen
per generar claus dâidentificaciĂł, requereixen un valor lĂČgic dâencesa constant per tal
dâassegurar una resposta fiable del PUF. Per aquest motiu, normalment es necessita
algun tipus de postprocessament per corregir els possibles errors presents en la resposta
del PUF. Malauradament, les cel·les que presenten una resposta més constant són
difĂcils de detectar a priori.
Aquest treball caracteritza per simulaciĂł la reproductibilitat del valor dâencesa de cel·les
SRAM, i proposa diverses mĂštriques per estimar la fiabilitat de les cel·les durant les fases de disseny de la memĂČria. L'objectiu Ă©s ser capaç de predir per simulaciĂł el percentatge
de cel·les que seran adequades per ser utilitzades com PUF. Sâavaluen els resultats de
diverses mĂštriques i sâanalitza la reproductibilitat dels valors dâencesa de les cel·les
considerant diverses fonts de pertorbacions externes, com diferents rampes de tensiĂł
per a lâencesa, els valors interns emmagatzemats prĂšviament en les cel·les, i diferents
temperatures. Es proposa utilitzar aquestes mÚtriques per estimar el nombre de cel·les
SRAM adients per ser implementades com a PUF en un disseny dâSRAM especĂfic.[spa] En la era de la Internet de las cosas (IoT), garantizar la seguridad del hardware se ha
convertido en un tema de investigaciĂłn crucial, en especial a causa de la creciente
demanda de productos electrónicos que se conectan remotamente a través de redes.
Para mejorar la seguridad de los sistemas IoT, se han propuesto nuevas soluciones
hardware basadas en la variabilidad de los procesos de fabricaciĂłn. Las funciones
fĂsicamente inclonables (PUF) constituyen una fuente fiable de aleatoriedad fĂsica y son
una base esencial para la seguridad hardware.
Las memorias SRAM se estĂĄn convirtiendo en una de las alternativas mĂĄs prometedoras
para la implementaciĂłn de funciones fĂsicamente inclonables empotradas. Esto es asĂ,
puesto que el valor de encendido de cada una de las celdas que forman los bits de la
memoria depende en gran medida de la variabilidad propia del proceso de fabricaciĂłn.
No todos los bits tienen el mismo grado de variabilidad. AsĂ pues, algunas celdas cambian
su estado lĂłgico de encendido de forma aleatoria entre encendidos, mientras que otras
siempre adquieren el mismo valor en todos los encendidos. Sin embargo, las funciones
fĂsicamente inclonables, que se utilizan para generar claves de identificaciĂłn, requieren
un valor lĂłgico de encendido constante para asegurar una respuesta fiable del PUF. Por
este motivo, normalmente se necesita algĂșn tipo de posprocesado para corregir los
posibles errores presentes en la respuesta del PUF. Desafortunadamente, las celdas que
presentan una respuesta mĂĄs constante son difĂciles de detectar a priori.
Este trabajo caracteriza por simulaciĂłn la reproductibilidad del valor de encendido de
celdas SRAM, y propone varias métricas para estimar la fiabilidad de las celdas durante las fases de diseño de la memoria. El objetivo es ser capaz de predecir por simulación el
porcentaje de celdas que serĂĄn adecuadas para ser utilizadas como PUF. Se evalĂșan los
resultados de varias métricas y se analiza la reproductibilidad de los valores de
encendido de las celdas considerando varias fuentes de perturbaciones externas, como
diferentes rampas de tensiĂłn para el encendido, los valores internos almacenados
previamente en las celdas, y diferentes temperaturas. Se propone utilizar estas métricas
para estimar el nĂșmero de celdas SRAM adecuadas para ser implementadas como PUF
en un diseño de SRAM especĂfico
Impact of atomistic device variability on analogue circuit design
Scaling of complementary metal-oxide-semiconductor (CMOS) technology has benefited the semiconductor industry for almost half a century. For CMOS devices with a physical gate-length in the sub-100 nm range, extreme device variability is introduced and has become a major stumbling block for next generation analogue circuit design. Both opportunities and challenges have therefore confronted analogue circuit designers. Small geometry device can enable high-speed analogue circuit designs, such as data conversion interfaces that can work in the radio frequency range. These designs can be co-integrated with digital systems to achieve low cost, high-performance, single-chip solutions that could only be achieved using multi-chip solutions in the past. However, analogue circuit designs are extremely vulnerable to device mismatch, since a large number of symmetric transistor pairs and circuit cells are required. The increase in device variability from sub-100 nm processes has therefore significantly reduced the production yield of the conventional designs.
Mismatch models have been developed to analytically evaluate the magnitude of random variations. Based on measurements from custom designed test structures, the statistics of process variation can be estimated using design related parameters. However, existing models can no longer accurately estimate the magnitude of mismatch for sub-100 nm âatomisticâ devices, since short-channel effects have become important. In this thesis, a new mismatch model for small geometry devices will be proposed to address this problem.
Based on knowledge of the matching performance obtained from the mismatch model, design solutions are desired at different design levels for a variety of circuit topologies. In this thesis, transistor level compensation solutions have been investigated and closed-loop compensation circuits have been proposed. At circuit level, a latch-based comparator has been used to develop a compensation solution because this type of comparator is extremely sensitive to the device mismatch. These comparators are also used as the fundamental building block for the analogue-to-digital converters (ADC). The proposed comparator compensation scheme is used to improve the performance of a high-speed flash ADC
Circuit Design
Circuit Design = Science + Art! Designers need a skilled "gut feeling" about circuits and related analytical techniques, plus creativity, to solve all problems and to adhere to the specifications, the written and the unwritten ones. You must anticipate a large number of influences, like temperature effects, supply voltages changes, offset voltages, layout parasitics, and numerous kinds of technology variations to end up with a circuit that works. This is challenging for analog, custom-digital, mixed-signal or RF circuits, and often researching new design methods in relevant journals, conference proceedings and design tools unfortunately gives the impression that just a "wild bunch" of "advanced techniques" exist. On the other hand, state-of-the-art tools nowadays indeed offer a good cockpit to steer the design flow, which include clever statistical methods and optimization techniques.Actually, this almost presents a second breakthrough, like the introduction of circuit simulators 40 years ago! Users can now conveniently analyse all the problems (discover, quantify, verify), and even exploit them, for example for optimization purposes. Most designers are caught up on everyday problems, so we fit that "wild bunch" into a systematic approach for variation-aware design, a designer's field guide and more. That is where this book can help! Circuit Design: Anticipate, Analyze, Exploit Variations starts with best-practise manual methods and links them tightly to up-to-date automation algorithms. We provide many tractable examples and explain key techniques you have to know. We then enable you to select and setup suitable methods for each design task - knowing their prerequisites, advantages and, as too often overlooked, their limitations as well. The good thing with computers is that you yourself can often verify amazing things with little effort, and you can use software not only to your direct advantage in solving a specific problem, but also for becoming a better skilled, more experienced engineer. Unfortunately, EDA design environments are not good at all to learn about advanced numerics. So with this book we also provide two apps for learning about statistic and optimization directly with circuit-related examples, and in real-time so without the long simulation times. This helps to develop a healthy statistical gut feeling for circuit design. The book is written for engineers, students in engineering and CAD / methodology experts. Readers should have some background in standard design techniques like entering a design in a schematic capture and simulating it, and also know about major technology aspects
An Energy-Efficient, Dynamic Voltage Scaling Neural Stimulator for a Proprioceptive Prosthesis
Accepted versio
Circuit Design
Circuit Design = Science + Art! Designers need a skilled "gut feeling" about circuits and related analytical techniques, plus creativity, to solve all problems and to adhere to the specifications, the written and the unwritten ones. You must anticipate a large number of influences, like temperature effects, supply voltages changes, offset voltages, layout parasitics, and numerous kinds of technology variations to end up with a circuit that works. This is challenging for analog, custom-digital, mixed-signal or RF circuits, and often researching new design methods in relevant journals, conference proceedings and design tools unfortunately gives the impression that just a "wild bunch" of "advanced techniques" exist. On the other hand, state-of-the-art tools nowadays indeed offer a good cockpit to steer the design flow, which include clever statistical methods and optimization techniques.Actually, this almost presents a second breakthrough, like the introduction of circuit simulators 40 years ago! Users can now conveniently analyse all the problems (discover, quantify, verify), and even exploit them, for example for optimization purposes. Most designers are caught up on everyday problems, so we fit that "wild bunch" into a systematic approach for variation-aware design, a designer's field guide and more. That is where this book can help! Circuit Design: Anticipate, Analyze, Exploit Variations starts with best-practise manual methods and links them tightly to up-to-date automation algorithms. We provide many tractable examples and explain key techniques you have to know. We then enable you to select and setup suitable methods for each design task - knowing their prerequisites, advantages and, as too often overlooked, their limitations as well. The good thing with computers is that you yourself can often verify amazing things with little effort, and you can use software not only to your direct advantage in solving a specific problem, but also for becoming a better skilled, more experienced engineer. Unfortunately, EDA design environments are not good at all to learn about advanced numerics. So with this book we also provide two apps for learning about statistic and optimization directly with circuit-related examples, and in real-time so without the long simulation times. This helps to develop a healthy statistical gut feeling for circuit design. The book is written for engineers, students in engineering and CAD / methodology experts. Readers should have some background in standard design techniques like entering a design in a schematic capture and simulating it, and also know about major technology aspects
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