Performance evaluation of FPGA implementations of high-speed addition algorithms

Driven by the excellent properties of FPGAs and the need for high-performance and flexible computing machines, interest in FPGA-based computing machines has increased dramatically. Fixed-point adders are essential building blocks of any computing systems. In this work, various high-speed addition algorithms are implemented in FPGAs devices, and their performance is evaluated with the objective of finding and developing the most appropriate addition algorithms for implementing in FPGAs, and laying the ground-work for evaluating and constructing FPGA-based computing machines. The results demonstrate that the performance of adders built with the FPGAs dedicated carry logic combined with some other addition algorithms will be greatly improved, especially for larger adders.published_or_final_versio

Tao--an architecturally balanced reconfigurable hardware processor

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1997.Includes bibliographical references (p. 107-109).This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.by Andrew S. Huang.M.Eng

Development and Evaluation of Sensor Concepts for Ageless Aerospace Vehicles: Report 5 - Phase 2 Implementation of the Concept Demonstrator

This report describes the second phase of the implementation of the Concept Demonstrator experimental test-bed system containing sensors and processing hardware distributed throughout the structure, which uses multi-agent algorithms to characterize impacts and determine a suitable response to these impacts. This report expands and adds to the report of the first phase implementation. The current status of the system hardware is that all 192 physical cells (32 on each of the 6 hexagonal prism faces) have been constructed, although only four of these presently contain data-acquisition sub-modules to allow them to acquire sensor data. Impact detection.. location and severity have been successfully demonstrated. The software modules for simulating cells and controlling the test-bed are fully operational. although additional functionality will be added over time. The visualization workstation displays additional diagnostic information about the array of cells (both real and simulated) and additional damage information. Local agent algorithms have been developed that demonstrate emergent behavior of the complex multi-agent system, through the formation of impact damage boundaries and impact networks. The system has been shown to operate well for multiple impacts. and to demonstrate robust reconfiguration in the presence of damage to numbers of cells

Row crop navigation by autonomous ground vehicle for crop scouting

Master of ScienceDepartment of Biological & Agricultural EngineeringDaniel FlippoRobotic vehicles have the potential to play a key role in the future of agriculture. For this to happen designs that are cost effective, robust, and easy to use will be necessary. Robotic vehicles that can pest scout, monitor crop health, and potentially plant and harvest crops will provide new ways to increase production within agriculture. At this time, the use of robotic vehicles to plant and harvest crops poses many challenges including complexity and power consumption. The incorporation of small robotic vehicles for monitoring and scouting fields has the potential to allow for easier integration of robotic systems into current farming practices as the technology continues to develop. Benefits of using unmanned ground vehicles (UGVs) for crop scouting include higher resolution and real time mapping, measuring, and monitoring of pest location density, crop nutrient levels, and soil moisture levels. The focus of this research is the ability of a UGV to scout pest populations and pest patterns to complement existing scouting technology used on UAVs to capture information about nutrient and water levels. There are many challenges to integrating UGVs in conventionally planted fields of row crops including intra-row and inter-row maneuvering. For intra-row maneuvering; i.e. between two rows of corn, cost effective sensors will be needed to keep the UGV between straight rows, to follow contoured rows, and avoid local objects. Inter-row maneuvering involves navigating from long straight rows to the headlands by moving through the space between two plants in a row. Oftentimes headland rows are perpendicular to the row that the UGV is within and if the crop is corn, the spacing between plants can be as narrow as 5”. A vehicle design that minimizes or eliminates crop damage when inter-row maneuvering occurs will be very beneficial and allow for earlier integration of robotic crop scouting into conventional farming practices. Using three fixed HC-SR04 ultrasonic sensors with LabVIEW programming proved to be a cost effective, simple, solution for intra-row maneuvering of an unmanned ground vehicle through a simulated corn row. Inter-row maneuvering was accomplished by designing a transformable tracked vehicle with the two configurations of the tracks being parallel and linear. The robotic vehicle operates with tracks parallel to each other and skid steering being the method of control for traveling between rows of corn. When the robotic vehicle needs to move through narrow spaces or from one row to the next, two motors rotate the frame of the tracks to a linear configuration where one track follows the other track. In the linear configuration the vehicle has a width of 5 inches which allows it to move between corn plants in high population fields for minimally invasive maneuvers. Fleets of robotic vehicles will be required to perform scouting operations on large fields. Some robotic vehicle operations will require coordination between machines to complete the tasks assigned. Simulation of the path planning for coordination of multiple machines was studied within the context of a non-stationary traveling salesman problem to determine optimal path plans

Liquid Cybernetic Systems: The Fourth‐Order Cybernetics

Technological development in robotics, computing architectures and devices, and information storage systems, in one single word: cybernetic systems, has progressed according to a jeopardized connection scheme, difficult if not impossible to track and picture in all its streams. Aim of this progress report is to critically introduce the most relevant limits and present a promising paradigm that might bring new momentum, offering features that naturally and elegantly overcome current challenges and introduce several other advantages: liquid cybernetic systems. The topic describing the four orders of cybernetic systems identified so far is introduced, evidencing the features of the fourth order that includes liquid systems. Then, current limitations to the development of conventional, von Neumann‐based cybernetic systems are briefly discussed: device integration, thermal design, data throughput, and energy consumption. In the following sections, liquid‐state machines are introduced, providing a computational paradigm (free from in materio considerations) that goes into the direction of solving such issues. Two original in materio implementation schemes are proposed: the COlloIdal demonsTratOR (COgITOR) autonomous robot, and a soft holonomic processor that is also proposed to realize an autolographic system

Internet Predictions

More than a dozen leading experts give their opinions on where the Internet is headed and where it will be in the next decade in terms of technology, policy, and applications. They cover topics ranging from the Internet of Things to climate change to the digital storage of the future. A summary of the articles is available in the Web extras section

Design and Implementation of a Software Defined Ionosonde. A contribution to the development of distributed arrays of small instruments

In order to make advances in studies of mesoscale ionospheric phenomena, a new type of ionosonde is needed. This ionosonde should be relatively inexpensive and small form factor. It should also be well suited for operation in a network of transmit and receiver sites that are operated cooperatively in order to measure vertical and oblique paths between multiple transmitters and receivers in the network. No such ionosonde implementation currently exists. This thesis describes the design and implementation of a coded continuous wave ionosonde, which utilizes long pseudo-random transmit waveforms. Such radar waveforms have several advantages: they can be used at low peak power, they can be used in multi-static cooperative radar networks, they can be used to measure range-Doppler overspread targets, they are relatively robust against external interference, and they produce relatively low interference to other users that share the same portion of the electromagnetic spectrum. The new ionosonde design is thus well suited for use in ionosonde networks. The technical design relies on the software defined radio paradigm and the hardware design is based on commercially available inexpensive hardware. The hardware and software implementation is shown to meet the technical and scientific requirements that were set for the instrument. The operation of the instrument is demonstrated in practice in Longyearbyen, Svalbard. With this new ionosonde design and proof of concept implementation, it has been possible to re-establish routine ionospheric soundings at Longyearbyen, Svalbard; to replace the Dynasonde instrument that was decommissioned several years ago. It is also possible to use this new design as a basis for larger networks of ionosondes. The software and hardware design is made publicly available as open source, so that anyone interested can reproduce the instrument and also contribute to the project in the future

Design of Hardware with Quantifiable Security against Reverse Engineering

Semiconductors are a 412 billion dollar industry and integrated circuits take on important roles in human life, from everyday use in smart-devices to critical applications like healthcare and aviation. Saving today\u27s hardware systems from attackers can be a huge concern considering the budget spent on designing these chips and the sensitive information they may contain. In particular, after fabrication, the chip can be subject to a malicious reverse engineer that tries to invasively figure out the function of the chip or other sensitive data. Subsequent to an attack, a system can be subject to cloning, counterfeiting, or IP theft. This dissertation addresses some issues concerning the security of hardware systems in such scenarios. First, the issue of privacy risks from approximate computing is investigated in Chapter 2. Simulation experiments show that the erroneous outputs produced on each chip instance can reveal the identity of the chip that performed the computation, which jeopardizes user privacy. The next two chapters deal with camouflaging, which is a technique to prevent reverse engineering from extracting circuit information from the layout. Chapter 3 provides a design automation method to protect camouflaged circuits against an adversary with prior knowledge about the circuit\u27s viable functions. Chapter 4 provides a method to reverse engineer camouflaged circuits. The proposed reverse engineering formulation uses Boolean Satisfiability (SAT) solving in a way that incorporates laser fault injection and laser voltage probing capabilities to figure out the function of an aggressively camouflaged circuit with unknown gate functions and connections. Chapter 5 addresses the challenge of secure key storage in hardware by proposing a new key storage method that applies threshold-defined behavior of memory cells to store secret information in a way that achieves a high degree of protection against invasive reverse engineering. This approach requires foundry support to encode the secrets as threshold voltage offsets in transistors. In Chapter 6, a secret key storage approach is introduced that does not rely on a trusted foundry. This approach only relies on the foundry to fabricate the hardware infrastructure for key generation but not to encode the secret key. The key is programmed by the IP integrator or the user after fabrication via directed accelerated aging of transistors. Additionally, this chapter presents the design of a working hardware prototype on PCB that demonstrates this scheme. Finally, chapter 7 concludes the dissertation and summarizes possible future research

A Hybrid Hardware/Software Architecture That Combines a 4-wide Very Long Instruction Word Software Processor (VLIW) with Application-specific Super-complex Instruction Set Hardware Functions

Application-driven processor designs are becoming increasingly feasible. Today, advances in field-programmable gate array (FPGA) technology are opening the doors to fast and highly-feasible hardware/software co-designed architectures. Over 100,000 FPGA logic array blocks and nearly 100 ASIC multiply-accumulate cores combine with extensible CPU cores to foster the design of configurable, application-driven hybrid processors.This thesis proposes a hardware/software co-designed architecture targeted to an FPGA. The architecture is a very-long instruction-word (VLIW) processor coupled with super-complex instruction set (SuperCISC) hardware co-processors. Results of the VLIW/SuperCISC show performance speedups over a single-issue processor of 9x to 332x, and entire application speedups from 4x to 127x. Contributions of this research include a 4-way VLIW designed from the ground up, a zero-overhead implementation of a hardware/software interface, evaluation of the scalability of shared data stores, examples of application-specific hardware accelerants, a SystemC simulator, and an evaluation of shared memory configurations