IR-Level Versus Machine-Level If-Conversion for Predicated Architectures

If-conversion is a simple yet powerful optimization that converts control dependences into data dependences. It allows elimination of branches and increases available instruction level parallelism and thus overall performance. If-conversion can either be applied alone or in combination with other techniques that increase the size of scheduling regions. The presence of hardware support for predicated execution allows if-conversion to be broadly applied in a given program. This makes it necessary to guide the optimization using heuristic estimates regarding its potential benefit. Similar to other transformations in an optimizing compiler, if-conversion inherently su↵ers from phase ordering issues. Driven by these facts, we developed two algorithms for if-conversion targeting the TI TMS320C64x+ architecture within the LLVM framework. Each implementation targets a di↵erent level of code abstraction. While one targets the intermediate representation, the other addresses machine-level code. Both make use of an adapted set of estimation heuristics and prove to be successful in general, but each one exhibits di↵erent strengths and weaknesses. High-level if-conversion, applied before other control flow transformations, has more freedom to operate. But in contrast to its machine-level counterpart, which is more restricted, its estimations of runtime are less accurate. Our results from experimental evaluation show a mean speedup close to 14 % for both algorithms on a set of programs from the MiBench and DSPstone benchmark suites. We give a comparison of the implemented optimizations and discuss gained insights on the topics of ifconversion, phase ordering issues and profitability analysis

Exploiting Conditional Instructions in Code Generation for Embedded VLIW Processors

This paper presents a new code optimization technique for a class of embedded processors. Modern embedded processor architectures show deep instruction pipelines and highly parallel VLIW-like instruction sets. For such architectures, any change in the control flow of a machine program due to a conditional jump may cause a significant code performance penalty. Therefore, the instruction sets of recent VLIW machines offer support for branch-free execution of conditional statements in the form of so-called conditional instructions. Whether an if-then-else statement is implemented by a conditional jump scheme or by conditional instructions has a strong impact on its worst-case execution time. However, the optimal selection is difficult particularly for nested conditionals. We present a dynamic programming technique for selecting the fastest implementation for nested if-then-else statements based on estimations. The efficacy is demonstrated for a real-life VLIW DSP. 1 1 Introduction A maj..

Exploiting Conditional Instructions in Code Generation for Embedded VLIW Processors

Abstract – This paper presents a new code optimization technique for a class of embedded processors. Modern embedded processor architectures show deep instruction pipelines and highly parallel VLIW-like instruction sets. For such architectures, any change in the control flow of a machine program due to a conditional jump may cause a significant code performance penalty. Therefore, the instruction sets of recent VLIW machines offer support for branch-free execution of conditional statements in the form of so-called conditionalinstructions. Whether an if-then-else statement is implemented by a conditional jump scheme or by conditional instructions has a strong impact on its worst-case execution time. However, the optimal selection is difficult particularly for nested conditionals. We present a dynamic programming technique for selecting the fastest implementation for nested if-then-else statements based on estimations. The efficacy is demonstrated for a real-life VLIW DSP. 1

Geração e vetorização de instruções de multiplicação e acumulação para processadores DSP SIMD

Orientador : Guido Costa Souza de AraujoDissertação (mestrado) - Universidade Estadual de Campinas, Instituto de ComputaçãoResumo: Processadores que são projetados para executar aplicações específicas - em oposição a processadores de propósito geral- representam uma porcentagem cada vez maior do total de processadores vendidos anualmente. Esses processadores são utilizados em aparelhos eletrônicos como telefones celulares e câmeras digitais, dispositivos médicos de monitoração, modems, sistemas militares de radar, componentes eletrônicos de automóveis, set-top boxes, etc. As aplicações que são executadas por esses processadores tipicamente demandam um alto desempenho, combinado com reduzido tamanho de código e dissipação de energia. Esta dissertação aborda um dos problemas presentes durante a geração de código para uma classe desses processadores, os processadores de sinais digitais (DSPs): como o compilador pode utilizar as instruções especializadas desses processadores a fim de aumentar a densidade e melhorar o desempenho do código gerado. É proposto um procedimento que permite a detecçãoj geração de instruções de multiplicação e acumulação (muito comuns nas aplicações desses processadores). É ainda apresentado um método que permite explorar a possibilidade de execução de código em paralelo por duas ou mais unidades funcionais quando essas são capazes de operar simultaneamente sobre diferentes dados. Os métodos aqui apresentados permitem uma exploração bastante agressiva das instruções de multiplicação e acumulação, e se utilizam de algoritmos de análise de fluxo de dados e técnicas de reestruturação de laços. Não é conhecido nenhum trabalho que aborde esse problema da maneira como é apresentada nesteAbstract: Application specific processors - as opposed to general purpose processors - account for an ever increasing percentage of the processors sold each year. These processors are widely used in electronic devices such as cellular phones and digital cameras, medical monitoring devices, modems, military radar systems, electronic components in vehicles and set-top boxes, to name a few. The applications that usually run on these processors demand high performance, reduced code size and low power consuption. This thesis addresses one of the issues that arise when generating code for a class of these processors, the digital signal processors (DSPs): how the compiler can take advantage of their specialized instructions in order to reduce the size and improve performance of the code generated. A method is proposed that allows for the detectionj generation of multiply and accumulate instructions (typically present in these processors' applications). AIso presented in this work is a method that makes it possible to explore the possibility of running code in parallel on two or more functional units when these are capable of operating simultaneously on different data. The methods herein presented allow for an aggressive harnessing of multiply and accumulate instructions; to accomplish this goal they rely on data flow analysis algorithms and on loop restructuring techniques. No other work is known of that addresses this problem the way it is dealt with in this thesisMestradoMestre em Ciência da Computaçã