An Evolvable Combinational Unit for FPGAs

A complete hardware implementation of an evolvable combinational unit for FPGAs is presented. The proposed combinational unit consisting of a virtual reconfigurable circuit and evolutionary algorithm was described in VHDL independently of a target platform, i.e. as a soft IP core, and realized in the COMBO6 card. In many cases the unit is able to evolve (i.e. to design) the required function automatically and autonomously, in a few seconds, only on the basis of interactions with an environment. A number of circuits were successfully evolved directly in the FPGA, in particular, 3-bit multipliers, adders, multiplexers and parity encoders. The evolvable unit was also tested in a simulated dynamic environment and used to design various circuits specified by randomly generated truth tables

High level optimizations in compiling process descriptions to asynchronous circuits

technical reportAsynchronous/'Self-Timed designs are beginning to attract attention as promising means of dealing with the complexity of modern VLSI technology. In this paper, we present our views on why asynchronous systems matter. We then present details of our high level synthesis tool SHILPA that can automatically synthesize asynchronous circuits from descriptions in our concurrent programming language, hopCP. We outline some of the high level communication abstractions available in hopCP. We illustrate how these abstractions are realized in the asynchronous circuits generated by SHILPA. We then present a series of examples that present many of the high level optimization strategies used by SHILPA. Some of these optimizations aim to speed up the generated circuits by avoiding un-necessary waiting. Others synthesize components that are much easier to realize in a variety of technologies. We also discuss some of the tradeoffs possible between optimizations and timing constraints

A circuit based Evolvable Hardware Architecture

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006.Includes bibliographical references (p. 69-72).This thesis presents an Evolvable Hardware Architecture that was developed in the Quantum Nanostructures and Nanofabrication Laboratory. We believe intrinsic evolution is a promising tool that can be used to exploit the physics of complex systems. I present a reconfigurable analog circuit platform that is coupled with a genetic algorithm to evolve circuit functions. The design process is detailed along with the results of three evolved circuits. Our coarse grained analog system parallels other evolvable hardware platforms that have been developed using the same architecture. I place our platform in the context of other efforts in the field and our intentions for future work. The speed and complexity of our board is discussed with areas for future development outlined.by Delano Christopher Sanchez.S.M

Evolving circuits on a field programmable analog array using genetic programming

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005.Includes bibliographical references (p. 57-60).This thesis describes the design and implementation of the Genetic Programming Intrinsic Circuit (GPIC) design system. Inspired by a number of recent advances in the field of Evolvable Hardware, the intended purpose of GPIC is to automate the design of analog circuits with minimal domain knowledge, computational resources, and cost using Genetic Programming with candidate solutions implemented in real hardware. This system has been constructed out of commercially available hardware and software, and the components were integrated through the development of a modular device-independent software system. The fitness evaluations of the candidate solutions of the Genetic Programming module are realized through a C interface to a National Instruments Data Acquisition Card. This Genetic Programming approach to analog circuit design decreases the fitness evaluation time of previous approaches by substituting expensive circuit simulation for real-time hardware testing. Since performing fitness evaluations in simulation is limited by the known model for a given environment, intrinsic testing provides additional benefit through the inherent incorporation of any unknown environmental conditions during tests. This feature is especially important for autonomous systems in unknown environments, and systems that must perform well in extreme environments.by Michael A. Terry.M.Eng

FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration

The FASTER (Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration) EU FP7 project, aims to ease the design and implementation of dynamically changing hardware systems. Our motivation stems from the promise reconfigurable systems hold for achieving high performance and extending product functionality and lifetime via the addition of new features that operate at hardware speed. However, designing a changing hardware system is both challenging and time-consuming. FASTER facilitates the use of reconfigurable technology by providing a complete methodology enabling designers to easily specify, analyze, implement and verify applications on platforms with general-purpose processors and acceleration modules implemented in the latest reconfigurable technology. Our tool-chain supports both coarse- and fine-grain FPGA reconfiguration, while during execution a flexible run-time system manages the reconfigurable resources. We target three applications from different domains. We explore the way each application benefits from reconfiguration, and then we asses them and the FASTER tools, in terms of performance, area consumption and accuracy of analysis