Development of Urban Electric Bus Drivetrain

The development of the drivetrain for a new series of urban electric buses is presented in the paper. The traction and design properties of several drive variants are compared. The efficiency of the drive was tested using simulation calculations of the vehicle rides based on data from real bus lines in Prague. The results of the design work and simulation calculations are presented in the paper

High Performance IIR Filter FPGA Implementation Utilizing SOS Microcode Core

This paper discusses the methods of optimal IIR filter FPGA implementation. The methods are focused on the reduction of occupied resources and increasing data throughput. Higher demands on an internal controller complexity are successfully solved by utilizing programmable microcode controller. The novelty of SOS core and its capabilities are presented and different variants of SOS core are assessed. The workflow of IIR filter design using MATLAB considering rounded coefficient method is demonstrated

Performance Investigation of Digital Lowpass IIR Filter Based on Different Platforms

The work presented in this paper illuminates the design and simulation of a recursive or Infinite Impulse Response (IIR) filter. The proposed design algorithm employs the Genetic Algorithm to determine the filter coefficients to satisfy the required performance. The effectiveness of different platforms on filter design and performance has been studied in this paper. Three different platforms are considered to implement and verify the designed filter’s work through simulation. The first platform is the MATLAB/SIMULINK software package used to implement the Biquad form filter. This technique is the basis for the software implementation of the designed IIR filter. The HDL – Cosimulation technique is considered the second one; it inspired to take advantage of the existing tools in SIMULINK to convert the designed filter algorithm to the Very high-speed integrated circuit Hardware Description Language (VHDL) format. The System Generator is employed as the third technique, in which the designed filter is implemented as a hardware structure based on basic unit blocks provided by Xilinx System Generator. This technique facilitates the implementation of the designed filter in the FPGA target device. Simulation results show that the performance of the designed filter is remarkably reliable even with severe noise levels

KAVUAKA: a low-power application-specific processor architecture for digital hearing aids

The power consumption of digital hearing aids is very restricted due to their small physical size and the available hardware resources for signal processing are limited. However, there is a demand for more processing performance to make future hearing aids more useful and smarter. Future hearing aids should be able to detect, localize, and recognize target speakers in complex acoustic environments to further improve the speech intelligibility of the individual hearing aid user. Computationally intensive algorithms are required for this task. To maintain acceptable battery life, the hearing aid processing architecture must be highly optimized for extremely low-power consumption and high processing performance.The integration of application-specific instruction-set processors (ASIPs) into hearing aids enables a wide range of architectural customizations to meet the stringent power consumption and performance requirements. In this thesis, the application-specific hearing aid processor KAVUAKA is presented, which is customized and optimized with state-of-the-art hearing aid algorithms such as speaker localization, noise reduction, beamforming algorithms, and speech recognition. Specialized and application-specific instructions are designed and added to the baseline instruction set architecture (ISA). Among the major contributions are a multiply-accumulate (MAC) unit for real- and complex-valued numbers, architectures for power reduction during register accesses, co-processors and a low-latency audio interface. With the proposed MAC architecture, the KAVUAKA processor requires 16 % less cycles for the computation of a 128-point fast Fourier transform (FFT) compared to related programmable digital signal processors. The power consumption during register file accesses is decreased by 6 %to 17 % with isolation and by-pass techniques. The hardware-induced audio latency is 34 %lower compared to related audio interfaces for frame size of 64 samples.The final hearing aid system-on-chip (SoC) with four KAVUAKA processor cores and ten co-processors is integrated as an application-specific integrated circuit (ASIC) using a 40 nm low-power technology. The die size is 3.6 mm2. Each of the processors and co-processors contains individual customizations and hardware features with a varying datapath width between 24-bit to 64-bit. The core area of the 64-bit processor configuration is 0.134 mm2. The processors are organized in two clusters that share memory, an audio interface, co-processors and serial interfaces. The average power consumption at a clock speed of 10 MHz is 2.4 mW for SoC and 0.6 mW for the 64-bit processor.Case studies with four reference hearing aid algorithms are used to present and evaluate the proposed hardware architectures and optimizations. The program code for each processor and co-processor is generated and optimized with evolutionary algorithms for operation merging,instruction scheduling and register allocation. The KAVUAKA processor architecture is com-pared to related processor architectures in terms of processing performance, average power consumption, and silicon area requirements

Measurements, Models, Systems and Design

531 s.

Design of Digital Integrator for Rogowski Coil Sensor

The goal of this thesis is to create a well performed digital Rogowski coil integrator on PC for later implementation on FPGA, and the final filter is applied with fixed point arithmetic. Integrator’s design and optimization based on the specification provided by the company. During the implementation, the constraints of the hardware should be taken into account, and the design method needs to be verified by simulations and practical experiments and tests. There are two design phases to implementing the filter. The first phase is software implementation, the integrator is realized by creating the MATLAB and C models. The other phase is hardware realization. By software application, the filter could be simu-lated with targeted test benches. After the software application is verified, hardware implementation could be carried out if it is necessary. In this thesis, RTL model is de-rived from the C model via translating it with VHDL. Afterward, the integrator is im-plemented on FPGA board for practical field tests. From the tests, the validity, practicability of the Rogowski integrator have to be veri-fied from the perspective of both functionality and performance. The software imple-mentation of the integrator is capable of filtering different kinds of the input signals with reasonable and acceptable outputs. Meanwhile, in the practical application, the integrator performed well when dealing with various earth fault cases. All, in brief, this Rogowski integrator has to satisfy the standard of the design specification

On Applications of New Soft and Evolutionary Computing Techniques to Direct and Inverse Modeling Problems

Adaptive direct modeling or system identification and adaptive inverse modeling or channel equalization find extensive applications in telecommunication, control system, instrumentation, power system engineering and geophysics. If the plants or systems are nonlinear, dynamic, Hammerstein and multiple-input and multiple-output (MIMO) types, the identification task becomes very difficult. Further, the existing conventional methods like the least mean square (LMS) and recursive least square (RLS) algorithms do not provide satisfactory training to develop accurate direct and inverse models. Very often these (LMS and RLS) derivative based algorithms do not lead to optimal solutions in pole-zero and Hammerstein type system identification problem as they have tendency to be trapped by local minima. In many practical situations the output data are contaminated with impulsive type outliers in addition to measurement noise. The density of the outliers may be up to 50%, which means that about 50% of the available data are affected by outliers. The strength of these outliers may be two to five times the maximum amplitude of the signal. Under such adverse conditions the available learning algorithms are not effective in imparting satisfactory training to update the weights of the adaptive models. As a result the resultant direct and inverse models become inaccurate and improper. Hence there are three important issues which need attention to be resolved. These are : (i) Development of accurate direct and inverse models of complex plants using some novel architecture and new learning techniques. (ii) Development of new training rules which alleviates local minima problem during training and thus help in generating improved adaptive models. (iii) Development of robust training strategy which is less sensitive to outliers in training and thus to create identification and equalization models which are robust against outliers. These issues are addressed in this thesis and corresponding contribution are outlined in seven Chapters. In addition, one Chapter on introduction, another on required architectures and algorithms and last Chapter on conclusion and scope for further research work are embodied in the thesis. A new cascaded low complexity functional link artificial neural network (FLANN) structure is proposed and the corresponding learning algorithm is derived and used to identify nonlinear dynamic plants. In terms of identification performance this model is shown to outperform the multilayer perceptron and FLANN model. A novel method of identification of IIR plants is proposed using comprehensive learning particle swarm optimization (CLPSO) algorithm. It is shown that the new approach is more accurate in identification and takes less CPU time compared to those obtained by existing recursive LMS (RLMS), genetic algorithm (GA) and PSO based approaches. The bacterial foraging optimization (BFO) and PSO are used to develop efficient learning algorithms to train models to identify nonlinear dynamic and MIMO plants. The new scheme takes less computational effort, more accurate and consumes less input samples for training. Robust identification and equalization of complex plants have been carried out using outliers in training sets through minimization of robust norms using PSO and BFO based methods. This method yields robust performance both in equalization and identification tasks. Identification of Hammerstein plants has been achieved successfully using PSO, new clonal PSO (CPSO) and immunized PSO (IPSO) algorithms. Finally the thesis proposes a distributed approach to identification of plants by developing two distributed learning algorithms : incremental PSO and diffusion PSO. It is shown that the new approach is more efficient in terms of accuracy and training time compared to centralized PSO based approach. In addition a robust distributed approach for identification is proposed and its performance has been evaluated. In essence the thesis proposed many new and efficient algorithms and structure for identification and equalization task such as distributed algorithms, robust algorithms, algorithms for ploe-zero identification and Hammerstein models. All these new methods are shown to be better in terms of performance, speed of computation or accuracy of results

Low Power Circuits for Smart Flexible ECG Sensors

Cardiovascular diseases (CVDs) are the world leading cause of death. In-home heart condition monitoring effectively reduced the CVD patient hospitalization rate. Flexible electrocardiogram (ECG) sensor provides an affordable, convenient and comfortable in-home monitoring solution. The three critical building blocks of the ECG sensor i.e., analog frontend (AFE), QRS detector, and cardiac arrhythmia classifier (CAC), are studied in this research. A fully differential difference amplifier (FDDA) based AFE that employs DC-coupled input stage increases the input impedance and improves CMRR. A parasitic capacitor reuse technique is proposed to improve the noise/area efficiency and CMRR. An on-body DC bias scheme is introduced to deal with the input DC offset. Implemented in 0.35m CMOS process with an area of 0.405mm2, the proposed AFE consumes 0.9W at 1.8V and shows excellent noise effective factor of 2.55, and CMRR of 76dB. Experiment shows the proposed AFE not only picks up clean ECG signal with electrodes placed as close as 2cm under both resting and walking conditions, but also obtains the distinct -wave after eye blink from EEG recording. A personalized QRS detection algorithm is proposed to achieve an average positive prediction rate of 99.39% and sensitivity rate of 99.21%. The user-specific template avoids the complicate models and parameters used in existing algorithms while covers most situations for practical applications. The detection is based on the comparison of the correlation coefficient of the user-specific template with the ECG segment under detection. The proposed one-target clustering reduced the required loops. A continuous-in-time discrete-in-amplitude (CTDA) artificial neural network (ANN) based CAC is proposed for the smart ECG sensor. The proposed CAC achieves over 98% classification accuracy for 4 types of beats defined by AAMI (Association for the Advancement of Medical Instrumentation). The CTDA scheme significantly reduces the input sample numbers and simplifies the sample representation to one bit. Thus, the number of arithmetic operations and the ANN structure are greatly simplified. The proposed CAC is verified by FPGA and implemented in 0.18m CMOS process. Simulation results show it can operate at clock frequencies from 10KHz to 50MHz. Average power for the patient with 75bpm heart rate is 13.34W