The GBT: A proposed architecure for multi-Gb/s data transmission in high energy physics

The future upgrade of the LHC accelerator, the SLHC, will increase the beam luminosity by a factor of ten leading to a corresponding growth of the amounts of data to be treated by the data transmission and acquisition systems. The development of the GBT chipset addresses this issue providing a means to increase the bandwidth available to transmit data to and from the counting room. The GigaBit Transceiver (GBT) architecture will provide the support to transmit simultaneously the three types of information required to run an experiment in a hostile radiation environment over a multipurpose link. This paper describes the GBT link architecture and some aspects of its implementation. As this project is still in the specification phase, detailed features might change prior to the final silicon fabrication

White RHINO: a low-cost communications radar hardware platform

Includes bibliographical referencesThe Electromagnetic spectrum has always been a very expensive resource and hence, has not been accessible to everyone. Yet, it is under-utilized. The new Whitespace Technology standards provide an efficient way to use the spectrum. However, the concept of shared spectrum introduced by the Whitespace Technology promises to reduce the cost of accessing the spectrum by a huge margin. Also, because the standards utilize the television channels, the VHF and UHF frequencies facilitate wireless transmission over large distances. This has provided impetus to various application developers. Using Whitespace Technology for Communications Radar is one such novel application which has great benefits for the African scenario. Here, the population is scattered and infrastructure for navigation and tracking is inadequate. But, there is a shortage of low-cost commercially available hardware platforms tailored for the application. In order to boost Whitespace-based Communications Radar application development, the White RHINO(Reconfigurable Hardware Interface for computation and radio) hardware platform was developed. It aims to fill the gap of low-cost commercial hardware platforms available for Whitespace-based Communications Radar. Being a Communications Radar platform, the White RHINO had to be designed keeping the standards and regulating body norms as yardsticks. However, an achievable radar performance of the platform under various scenarios was also estimated. The White RHINO contains an FPGA (the Zynq7000 series) which has dual embedded ARM processing cores. For the wireless interface, it contains a field programmable RF transceiver and an RF frontend section. The platform contains wired networking capability of 2 Gbps. The platform also has 512 MB DDR3 and 128 Mbit NAND ash as onboard memory. Finally, it has USB host, SDIO and JTAG for programmability and temperature sensors for system monitoring. The manufactured boards were tested under lab environment. It was found that except a failure on the RF transceiver section (due to a PCB footprint error), other interfaces were functional. The White RHINO successfully runs both U-Boot and Linux as operating systems. The error and other minor bugs have been corrected for the next fabrication run. Also, the cost of the complete White RHINO system is less than 1000 USD which makes it a very powerful platform and yet, less expensive than most of the commercially available platforms designed for similar applications

Ethernet - a survey on its fields of application

During the last decades, Ethernet progressively became the most widely used local area networking (LAN) technology. Apart from LAN installations, Ethernet became also attractive for many other fields of application, ranging from industry to avionics, telecommunication, and multimedia. The expanded application of this technology is mainly due to its significant assets like reduced cost, backward-compatibility, flexibility, and expandability. However, this new trend raises some problems concerning the services of the protocol and the requirements for each application. Therefore, specific adaptations prove essential to integrate this communication technology in each field of application. Our primary objective is to show how Ethernet has been enhanced to comply with the specific requirements of several application fields, particularly in transport, embedded and multimedia contexts. The paper first describes the common Ethernet LAN technology and highlights its main features. It reviews the most important specific Ethernet versions with respect to each application field’s requirements. Finally, we compare these different fields of application and we particularly focus on the fundamental concepts and the quality of service capabilities of each proposal

Implementation of Ultra-Low Latency and High-Speed Communication Channels for an FPGA-Based HPC Cluster

RÉSUMÉ Les clusters basés sur les FPGA bénéficient de leur flexibilité et de leurs performances en termes de puissance de calcul et de faible consommation. Et puisque la consommation de puissance devient un élément de plus en plus importants sur le marché des superordinateurs, le domaine d’exploration multi-FPGA devient chaque année plus populaire. Les performances des ordinateurs n’ont jamais cessé d’augmenter mais la latence des réseaux d’interconnexion n’a pas suivi leur taux d’amélioration. Dans le but d’augmenter le niveau d’abstraction et les fonctionnalités des interconnexions, la complexité des piles de communication atteinte à nos jours engendre des coûts et affecte la latence des communications, ce qui rend ces piles de communication très souvent inefficaces, voire inutiles. Les protocoles de communication commerciaux existants et les contrôleurs d’interfaces réseau FPGA-FPGA n’ont la performance pour supporter ni les applications à temps critique ni un partitionnement étroitement couplé des systèmes sur puce. Au lieu de cela, les approches de communication personnalisées sont souvent préférées. Dans ce travail, nous proposons une implémentation de canaux de communication à haut débit et à faible latence pour une grappe de FPGA. Le système est constitué de deux BEE3, chacun contenant 4 FPGA de la famille Virtex-5 interconnectés par une topologie en anneau. Notre approche exploite la technologie à transducteur à plusieurs gigabits par seconde pour l’obtention d’une bande passante fiable de 8Gbps. Le module de propriété intellectuelle (IP) de communication proposé permet le transfert de données entre des milliers de coprocesseurs sur le réseau, grâce à l’implémentation d’un réseau direct avec capacité de routage de paquets. Les résultats expérimentaux ont montré une latence de seulement 34 cycles d’horloge entre deux noeuds voisins, ce qui est un des plus bas parmi ceux rapportés dans la littérature. En outre, nous proposons une architecture adaptée au calcul à haute performance qui comporte un traitement extensible, parallèle et distribué. Pour une plateforme à 8 FPGA, l’architecture fournit 35.6Go/s de bande passante effective pour la mémoire externe, une bande passante globale de réseau de 128Gbps et une puissance de calcul de 8.9GFLOPS. Un solveur matrice-vecteur de grande taille est partitionné et mis en oeuvre à travers le cluster. Nous avons obtenu une performance et une efficacité de calcul concurrentielles grâce à la faible empreinte du protocole de communication entre les éléments de traitement distribués. Ce travail contribue à soutenir de nouvelles recherches dans le domaine du calcul parallèle intensif et permet le partitionnement de système sur puce à grande taille sur des clusters à base de FPGA.----------ABSTRACT An FPGA-based cluster profits from the flexibility and the performance potential FPGA technology provides. Since price and power consumption are becoming increasingly important elements in the High-Performance Computing market, the multi-FPGA exploration field is getting more popular each year. Network latency has failed to keep up with other improvements in computer performance. Complex communication stacks have sacrificed latency and increased overhead to achieve other goals, being in most of the time inefficient and unnecessary. The existing commercial offthe- shelf communication protocols and Network Interfaces Controllers for FPGA-to-FPGA interconnection lack of performance to support time-critical applications and tightly coupled System-on-Chip partitioning. Instead, custom communication approaches are preferred. In this work, ultra-low latency and high-speed communication channels for an FPGA-based cluster are presented. Two BEE3s grouping 8 FPGAs Virtex-5 interconnected in a ring topology, compose the targeting platform. Our approach exploits Multi-Gigabit Transceiver technology to achieve reliable 8Gbps channel bandwidth. The proposed communication IP supports data transfer from coprocessors over the network, by means of a direct network implementation with hop-by-hop packet routing capability. Experimental results showed a latency of only 34 clock cycles between two neighboring nodes, being one of the lowest in the literature. In addition, it is proposed an architecture suitable for High-Performance Computing which includes performing scalable, parallel, and distributed processing. For an 8 FPGAs platform, the architecture provides 35.6GB/s off-chip memory throughput, 128Gbps network aggregate bandwidth, and 8.9GFLOPS computing power. A large and dense matrix-vector solver is partitioned and implemented across the cluster. We achieved competitive performance and computational efficiency as a result of the low communication overhead among the distributed processing elements. This work contributes to support new researches on the intense parallel computing fields, and enables large System-on-Chip partitioning and scaling on FPGA-based clusters

SpaceCube: A NASA Family of Reconfigurable Hybrid On-Board Science Data Processors

SpaceCube is a family of Field Programmable Gate Array (FPGA) based on-board science-data processing systems developed at NASA Goddard Space Flight Center. This presentation provides an overview to the Future In-Space Operations Telecon Working Group