Analysis of total dose-induced dark current in CMOS image sensors from interface state and trapped charge density measurements

The origin of total ionizing dose induced dark current in CMOS image sensors is investigated by comparing dark current measurements to interface state density and trapped charge density measurements. Two types of photodiode and several thick-oxide-FETs were manufactured using a 0.18-µm CMOS image sensor process and exposed to 10-keV X-ray from 3 krad to 1 Mrad. It is shown that the radiation induced trapped charge extends the space charge region at the oxide interface, leading to an enhancement of interface state SRH generation current. Isochronal annealing tests show that STI interface states anneal out at temperature lower than 100°C whereas about a third of the trapped charge remains after 30 min at 300°C

Generic radiation hardened photodiode layouts for deep submicron CMOS image sensor processes

Selected radiation hardened photodiode layouts, manufactured in a deep submicron CMOS Image Sensor technology, are irradiated by 60Co gamma-rays up to 2.2 Mrad(SiO2) and studied in order to identify the most efficient structures and the guidelines (recess distance, bias voltage) to follow to make them work efficiently in such technology. To do so, both photodiode arrays and active pixel sensors are used. After 2.2 Mrad(SiO2), the studied sensors are fully functional and most of the radiation hardened photodiodes exhibit radiation induced dark current values more than one order of magnitude lower than the standard photodiode

Ionizing radiation e\ufb00ects in nanoscale CMOS technologies exposed to ultra-high doses

This thesis studies the e\ufb00ects of radiation in nanoscale CMOS technologies exposed to ultra-high total ionizing doses (TID), up to 1 Grad(SiO2). These extreme radiation levels are orders of magnitude higher that those typically experienced by space applications (where radiation e\ufb00ects in electronic are of concern). However, they can be found in some speci\ufb01c applications like the large-hadron-collider (LHC) of CERN, and, in particular, in its future upgrade, the high-luminosity LHC (HL-LHC). The study at such high doses has both revealed new phenomena, and has contributed to a better understanding of some of the already known radiation-induced e\ufb00ects. The radiation response of four di\ufb00erent CMOS technology nodes, i.e., 130, 65, 40 and 28 nm, coming from di\ufb00erent manufacturers, has been investigated in di\ufb00erent conditions of temperature, bias, dose-rate and for di\ufb00erent transistor\u2019s sizes, providing an unique and comprehensive set of data about the ultra-high TID-induced phenomena in modern CMOS technologies. This study has con\ufb01rmed that the thin gate oxide of nanoscale technologies is extremely robust to radiation, even at ultra-high doses. The main cause of performance degradation has been identi\ufb01ed in the presence of auxiliary oxides such as shallow trench insulation oxides (STI) and spacers. Both radiation-induced drain-to-source leakage current increase and radiation-induced narrow channel e\ufb00ect (RINCE) are caused by positive charge trapped in the STI. In this work, thanks to exposures to very high TID levels and to measurements performed in di\ufb00erent conditions of temperature and bias, we show that the two e\ufb00ects are provoked by charge trapped in di\ufb00erent locations along the trench oxide. Moreover, a new unexpected ultra-high-dose drain current increase (UCLI) e\ufb00ect, a\ufb00ecting narrow and long nMOS transistors, has been observed. In-depth studies of the radiation-induced short channel e\ufb00ect (RISCE), related to the presence of the spacers, have shown that, at ultra-high doses, the degradation mechanism consists of two phases. A \ufb01rst increase of the series resistance, caused by the radiation-induced charge trapping in the spacers, is followed by a threshold voltage shift provoked by the transport of hydrogen ions from the spacers to the gate oxide. This model has been validated by several static measurements, TCAD simulations and charge pumping measurements. The dependencies of these e\ufb00ects on bias, temperature and size of the transistors have also been studied in detail. Moreover, an unexpected true dose-rate sensitivity has been measured in both nMOS and pMOS transistors in 65 and 130 nm technologies, although the radiation response of MOS devices is considered insensitive to true dose-rate e\ufb00ects. The current degradation in samples irradiated at a dose-rate comparable to that expected in the HL-LHC is larger by a factor of 3c2 than that measured in the typical quali\ufb01cation test, usually carried out with a much higher dose-rate. This is clearly of serious concern for the quali\ufb01cation of circuits designed for the particle detectors of the HL-LHC

Simulation study of scaling design, performance characterization, statistical variability and reliability of decananometer MOSFETs

This thesis describes a comprehensive, simulation based scaling study – including device design, performance characterization, and the impact of statistical variability – on deca-nanometer bulk MOSFETs. After careful calibration of fabrication processes and electrical characteristics for n- and p-MOSFETs with 35 nm physical gate length, 1 nm EOT and stress engineering, the simulated devices closely match the performance of contemporary 45 nm CMOS technologies. Scaling to 25 nm, 18 nm and 13 nm gate length n and p devices follows generalized scaling rules, augmented by physically realistic constraints and the introduction of high-k/metal-gate stacks. The scaled devices attain the performance stipulated by the ITRS. Device a.c. performance is analyzed, at device and circuit level. Extrinsic parasitics become critical to nano-CMOS device performance. The thesis describes device capacitance components, analyzes the CMOS inverter, and obtains new insights into the inverter propagation delay in nano-CMOS. The projection of a.c. performance of scaled devices is obtained. The statistical variability of electrical characteristics, due to intrinsic parameter fluctuation sources, in contemporary and scaled decananometer MOSFETs is systematically investigated for the first time. The statistical variability sources: random discrete dopants, gate line edge roughness and poly-silicon granularity are simulated, in combination, in an ensemble of microscopically different devices. An increasing trend in the standard deviation of the threshold voltage as a function of scaling is observed. The introduction of high-k/metal gates improves electrostatic integrity and slows this trend. Statistical evaluations of variability in Ion and Ioff as a function of scaling are also performed. For the first time, the impact of strain on statistical variability is studied. Gate line edge roughness results in areas of local channel shortening, accompanied by locally increased strain, both effects increasing the local current. Variations are observed in both the drive current, and in the drive current enhancement normally expected from the application of strain. In addition, the effects of shallow trench isolation (STI) on MOSFET performance and on its statistical variability are investigated for the first time. The inverse-narrow-width effect of STI enhances the current density adjacent to it. This leads to a local enhancement of the influence of junction shapes adjacent to the STI. There is also a statistical impact on the threshold voltage due to random STI induced traps at the silicon/oxide interface

High-Voltage Devices in Smart Power Technology

Tato práce se zabývá popisem základních vlastností LDMOS tranzistorů. V první části práce jsou rozebrány vlastnosti LDMOS tranzistorů, jejich základní parametry a techniky pro vylepšení parametrů těchto tranzistorů. V další části je rozebrána spolehlivost LDMOS tranzistorů, tato část popisuje bezpečnou pracovní oblast (SOA), injekci horkých nosičů (HCI) a negativní teplotní stabilitu (NBTI). Poslední teoretická část popisuje používané modely pro simulaci ESD událostí. Praktická část práce je zaměřena na simulaci základních parametrů PLDMOS a NLDMOS tranzistorů, porovnání simulovaných a změřených koncentračních profilů. Dále se práce zabývá simulacemi změny geometrických parametrů PLDMOS tranzistoru a vliv těchto změn na elektrické parametry. Poslední část práce tvoří TLP simulace, které zkoumají elektrické vlastnosti PLDMOS tranzistoru při použití jako ESD ochrana.This work describes fundamental characteristics of LDMOS transistors. In the first part of work are described properties of LDMOS transistors, the basic parameters and techniques to improve parameters of transistors. The next section discusses the reliability of LDMOS transistors. This section describes the safe operating area (SOA), hot carrier injection (HCI) and negative bias temperature instability (NBTI). The last theoretical section describes models used to simulate ESD events. The practical part is focused on simulation of the basic parameters PLDMOS and NLDMOS transistors and comparison of simulated and measured concentration profiles. Furthermore the thesis deals with simulation of the impact of changes in geometrical parameters of the PLDMOS transistor and the impact of these changes on the electrical parameters. The last part contains TLP simulations which examines electrical properties of PLDMOS transistor when is used as ESD protection.

Design and simulation of strained-Si/strained-SiGe dual channel hetero-structure MOSFETs

With a unified physics-based model linking MOSFET performance to carrier mobility and drive current, it is shown that nearly continuous carrier mobility increase has been achieved by introduction of process-induced and global-induced strain, which has been responsible for increase in device performance commensurately with scaling. Strained silicon-germanium technology is a hot research area, explored by many different research groups for present and future CMOS technology, due to its high hole mobility and easy process integration with silicon. Several heterostructure architectures for strained Si/SiGe have been shown in the literature. A dual channel heterostructure consisting of strained Si/Si1-xGex on a relaxed SiGe buffer provides a platform for fabricating MOS transistors with high drive currents, resulting from high carrier mobility and carrier velocity, due to presence of compressively strained silicon germanium layer. This works reports the design, modeling and simulation of NMOS and PMOS transistors with a tensile strained Si channel layer and compressively strained SiGe channel layer for a 65 nm logic technology node. Since most of the recent work on development of strained Si/SiGe has been experimental in nature, developments of compact models are necessary to predict the device behavior. A unified modeling approach consisting of different physics-based models has been formulated in this work and their ability to predict the device behavior has been investigated. In addition to this, quantum mechanical simulations were performed in order to investigate and model the device behavior. High p/n-channel drive currents of 0.43 and 0.98 mA/Gm, respectively, are reported in this work. However with improved performance, ~ 10% electrostatic degradation was observed in PMOS due to buried channel device

Modeling of Total Ionizing Dose Effects in Advanced Complementary Metal-Oxide-Semiconductor Technologies

abstract: The increased use of commercial complementary metal-oxide-semiconductor (CMOS) technologies in harsh radiation environments has resulted in a new approach to radiation effects mitigation. This approach utilizes simulation to support the design of integrated circuits (ICs) to meet targeted tolerance specifications. Modeling the deleterious impact of ionizing radiation on ICs fabricated in advanced CMOS technologies requires understanding and analyzing the basic mechanisms that result in buildup of radiation-induced defects in specific sensitive regions. Extensive experimental studies have demonstrated that the sensitive regions are shallow trench isolation (STI) oxides. Nevertheless, very little work has been done to model the physical mechanisms that result in the buildup of radiation-induced defects and the radiation response of devices fabricated in these technologies. A comprehensive study of the physical mechanisms contributing to the buildup of radiation-induced oxide trapped charges and the generation of interface traps in advanced CMOS devices is presented in this dissertation. The basic mechanisms contributing to the buildup of radiation-induced defects are explored using a physical model that utilizes kinetic equations that captures total ionizing dose (TID) and dose rate effects in silicon dioxide (SiO2). These mechanisms are formulated into analytical models that calculate oxide trapped charge density (Not) and interface trap density (Nit) in sensitive regions of deep-submicron devices. Experiments performed on field-oxide-field-effect-transistors (FOXFETs) and metal-oxide-semiconductor (MOS) capacitors permit investigating TID effects and provide a comparison for the radiation response of advanced CMOS devices. When used in conjunction with closed-form expressions for surface potential, the analytical models enable an accurate description of radiation-induced degradation of transistor electrical characteristics. In this dissertation, the incorporation of TID effects in advanced CMOS devices into surface potential based compact models is also presented. The incorporation of TID effects into surface potential based compact models is accomplished through modifications of the corresponding surface potential equations (SPE), allowing the inclusion of radiation-induced defects (i.e., Not and Nit) into the calculations of surface potential. Verification of the compact modeling approach is achieved via comparison with experimental data obtained from FOXFETs fabricated in a 90 nm low-standby power commercial bulk CMOS technology and numerical simulations of fully-depleted (FD) silicon-on-insulator (SOI) n-channel transistors.Dissertation/ThesisPh.D. Electrical Engineering 201

Total Dose Simulation for High Reliability Electronics

abstract: New technologies enable the exploration of space, high-fidelity defense systems, lighting fast intercontinental communication systems as well as medical technologies that extend and improve patient lives. The basis for these technologies is high reliability electronics devised to meet stringent design goals and to operate consistently for many years deployed in the field. An on-going concern for engineers is the consequences of ionizing radiation exposure, specifically total dose effects. For many of the different applications, there is a likelihood of exposure to radiation, which can result in device degradation and potentially failure. While the total dose effects and the resulting degradation are a well-studied field and methodologies to help mitigate degradation have been developed, there is still a need for simulation techniques to help designers understand total dose effects within their design. To that end, the work presented here details simulation techniques to analyze as well as predict the total dose response of a circuit. In this dissertation the total dose effects are broken into two sub-categories, intra-device and inter-device effects in CMOS technology. Intra-device effects degrade the performance of both n-channel and p-channel transistors, while inter-device effects result in loss of device isolation. In this work, multiple case studies are presented for which total dose degradation is of concern. Through the simulation techniques, the individual device and circuit responses are modeled post-irradiation. The use of these simulation techniques by circuit designers allow predictive simulation of total dose effects, allowing focused design changes to be implemented to increase radiation tolerance of high reliability electronics.Dissertation/ThesisPh.D. Electrical Engineering 201

Strain-Engineered MOSFETs

This book brings together new developments in the area of strain-engineered MOSFETs using high-mibility substrates such as SIGe, strained-Si, germanium-on-insulator and III-V semiconductors into a single text which will cover the materials aspects, principles, and design of advanced devices, their fabrication and applications. The book presents a full TCAD methodology for strain-engineering in Si CMOS technology involving data flow from process simulation to systematic process variability simulation and generation of SPICE process compact models for manufacturing for yield optimization