Characterization of the amplitude frequency response of Analog-to-Digital Converters

This paper describes a method for the characterization of the amplitude frequency response of Analog-to-Digital converters at frequencies up to 20 kHz using a true quantum reference calibrated semiconductor based DAC arbitrary waveform generator, developed within the EMPIR project Q-WAVE, jointly founded by the European Union and the partipating countries. The procedure that can be used for the characterization of any ADC is appplied to de DCV function of a Keysight 3458A digital multimeter. The measurement conditions an the main uncertainty sources are identified and evaluated for complete uncertainty estimation by means of the Monte Carlo Method

Josephson Wellenform Charakterisierung eines Sigma-Delta Analog/Digital Wandlers zur Datenerfassung in der Metrologie

A sampling system based on a 24-bits sigma-delta analog-to-digital converter (ADC) was built and characterized in order to study the feasibility of using this type of ADCs in electrical metrology. The non-linearities of the sampling system have been studied and a model for postcorrecting the measured data points established. The Hammerstein model, consisting of a static non-linear part and a linear system, was employed. A 4-th order polynomial accounts for the non-linearities of the analog electronics and the input stages of the sigma delta ADC. The linear part corresponds to the transfer function of the decimation filters internal to the ADC. The parameters for the model of the system were determined using noiseless and drift-free waveforms from a Josephson waveform synthesizer. The performance of the sampling system was verified experimentally by comparing the measured root-mean-square (rms) value of sinusoidal signals with the results from an established method. The results obtained using the post-corrected samples from the sampling system at 125 Hz agreed to within 2 μV/V with the de facto standard in metrology laboratories, which uses a high accuracy digital voltmeter. Precision measurements are limited by the decimation filters inside the ADC and can only be carried out for frequencies below 1/24-th of the equivalent sampling rate. The characterization results have shown that the non-linearities have been compensated to 5 μV/V or better and the effective resolution exceeds 20 bits, over an input range of 1 V at the equivalent sampling rate of 32 kHz. The experimental validation has proved that it is possible to measure rms values of sinusoidal signals with 1 V peak amplitudes for frequencies up to 1.3 kHz with uncertainty of 8 μV/V, significantly improving the uncertainty achievable with de facto standard which reaches 8 μV/V at 500 Hz.Ein Abtastsystem basierend auf einem 24-Bit Sigma-Delta Analog-DigitalWandler (ADC) wurde gebaut und charakterisiert, um die Möglichkeiten eines solchen ADC-Typs für Anwendungen in der elektrischen Metrologie zu untersuchen. Die Nichtlinearitäten des Abtastsystems wurden bestimmt und ein Modell für die nachträgliche Korrektur der erfassten Abtastwerte entwickelt. Dafür wurde das Hammerstein Modell verwendet, das zur Charakterisierung eines statisch, nichtlinearen Blocks gefolgt von einem linearen Teil geeignet ist. Ein Polynom vierter Ordnung wurde zur Beschreibung der statischen Nichtlinearität in der analogen Elektronik und der Eingangsstufe des Sigma-Delta ADC verwendet. Der lineare Teil des Modells umfasst die Transferfunktion des Dezimationsfilters im ADC Chip. Die Parameter für das Modell wurden mithilfe rausch- und driftloser Signale von einem Josephson Wellenform Synthesizer ermittelt. Die Leistungsfähigkeit des Abtastsystems wurde experimentell durch Effektivwertmessungen (rms) von sinusförmigen Signalen mit einem etablierten Messverfahren überprüft. Als Ergebnis wurde eine Übereinstimmung innerhalb von 2 μV/V bei 125 Hz mit dem de facto Normal der metrologischen Kalibrierlabore gefunden, das auf einem hochpräzisen Digitalvoltmeter basiert. Präzisionsmessungen haben ergeben, dass die Dezimationsfilter im ADC die maximale Frequenz auf 1/24stel der äquivalenten Abtastrate begrenzen, wenn die bestmöglichen Unsicherheiten erreicht werden sollen. Die Ergebnisse der Systemcharakterisierung haben bestätigt, dass Nichtlinearitäten auf 5 μV/V oder besser kompensiert werden. Die effektive Auflösung überschreitet 20 Bit über einen Eingangsbereich von 1 V und mit einer äquivalenten Abtastrate von 32 kHz. Die experimentelle Überprüfung hat gezeigt, dass es mit dem neuen System möglich ist, den Effektivwert sinusförmiger Signale und 1 V Amplitude für Frequenzen bis 1,3 kHz mit einer Messunsicherheit von 8 μV/V zu bestimmen, und somit die erreichbare Messunsicherheit des de facto Normals, das 8 μV/V bei 500 Hz erreicht, deutlich zu verbessern

Metrological characterization of sensors and instrumentation for distribution grid monitoring and electrical asset diagnostics

The Smart Grid needs a large amount of information to be operated and day by day new information is required to improve the operation performance. It is also fundamental that the available information is reliable and accurate. Therefore, the role of metrology is crucial, especially if applied to the distribution grid monitoring and the electrical assets diagnostics. This dissertation aims at better understanding the sensors and the instrumentation employed by the power system operators in the above-mentioned applications and studying new solutions. Concerning the research on the measurement applied to the electrical asset diagnostics: an innovative drone-based measurement system is proposed for monitoring medium voltage surge arresters. This system is described, and its metrological characterization is presented. On the other hand, the research regarding the measurements applied to the grid monitoring consists of three parts. The first part concerns the metrological characterization of the electronic energy meters’ operation under off-nominal power conditions. Original test procedures have been designed for both frequency and harmonic distortion as influence quantities, aiming at defining realistic scenarios. The second part deals with medium voltage inductive current transformers. An in-depth investigation on their accuracy behavior in presence of harmonic distortion is carried out by applying realistic current waveforms. The accuracy has been evaluated by means of the composite error index and its approximated version. Based on the same test setup, a closed-form expression for the measured current total harmonic distortion uncertainty estimation has been experimentally validated. The metrological characterization of a virtual phasor measurement unit is the subject of the third and last part: first, a calibrator has been designed and the uncertainty associated with its steady-state reference phasor has been evaluated; then this calibrator acted as a reference, and it has been used to characterize the phasor measurement unit implemented within a real-time simulator

Feasibility of Geiger-mode avalanche photodiodes in CMOS standard technologies for tracker detectors

The next generation of particle colliders will be characterized by linear lepton colliders, where the collisions between electrons and positrons will allow to study in great detail the new particle discovered at CERN in 2012 (presumably the Higgs boson). At present time, there are two alternative projects underway, namely the ILC (International Linear Collider) and CLIC (Compact LInear Collider). From the detector point of view, the physics aims at these particle colliders impose such extreme requirements, that there is no sensor technology available in the market that can fulfill all of them. As a result, several new detector systems are being developed in parallel with the accelerator. This thesis presents the development of a GAPD (Geiger-mode Avalanche PhotoDiode) pixel detector aimed mostly at particle tracking at future linear colliders. GAPDs offer outstanding qualities to meet the challenging requirements of ILC and CLIC, such as an extraordinary high sensitivity, virtually infinite gain and ultra-fast response time, apart from compatibility with standard CMOS technologies. In particular, GAPD detectors enable the direct conversion of a single particle event onto a CMOS digital pulse in the sub-nanosecond time scale without the utilization of either preamplifiers or pulse shapers. As a result, GAPDs can be read out after each single bunch crossing, a unique quality that none of its competitors can offer at the moment. In spite of all these advantages, GAPD detectors suffer from two main problems. On the one side, there exist noise phenomena inherent to the sensor, which induce noise pulses that cannot be distinguished from real particle events and also worsen the detector occupancy to unacceptable levels. On the other side, the fill-factor is too low and gives rise to a reduced detection efficiency. Solutions to the two problems commented that are compliant with the severe specifications of the next generation of particle colliders have been thoroughly investigated. The design and characterization of several single pixels and small arrays that incorporate some elements to reduce the intrinsic noise generated by the sensor are presented. The sensors and the readout circuits have been monolithically integrated in a conventional HV-CMOS 0.35 μm process. Concerning the readout circuits, both voltage-mode and current-mode options have been considered. Moreover, the time-gated operation has also been explored as an alternative to reduce the detected sensor noise. The design and thorough characterization of a prototype GAPD array, also monolithically integrated in a conventional 0.35 μm HV-CMOS process, is presented in the thesis as well. The detector consists of 10 rows x 43 columns of pixels, with a total sensitive area of 1 mm x 1 mm. The array is operated in a time-gated mode and read out sequentially by rows. The efficiency of the proposed technique to reduce the detected noise is shown with a wide variety of measurements. Further improved results are obtained with the reduction of the working temperature. Finally, the suitability of the proposed detector array for particle detection is shown with the results of a beam-test campaign conducted at CERN-SPS (European Organization for Nuclear Research-Super Proton Synchrotron). Apart from that, a series of additional approaches to improve the performance of the GAPD technology are proposed. The benefits of integrating a GAPD pixel array in a 3D process in terms of overcoming the fill-factor limitation are examined first. The design of a GAPD detector in the Global Foundries 130 nm/Tezzaron 3D process is also presented. Moreover, the possibility to obtain better results in light detection applications by means of the time-gated operation or correction techniques is analyzed too.Aquesta tesi presenta el desenvolupament d’un detector de píxels de GAPDs (Geiger-mode Avalanche PhotoDiodes) dedicat principalment a rastrejar partícules en futurs col•lisionadors lineals. Els GAPDs ofereixen unes qualitats extraordinàries per satisfer els requisits extremadament exigents d’ILC (International Linear Collider) i CLIC (Compact LInear Collider), els dos projectes per la propera generació de col•lisionadors que s’han proposat fins a dia d’avui. Entre aquestes qualitats es troben una sensibilitat extremadament elevada, un guany virtualment infinit i una resposta molt ràpida, a part de ser compatibles amb les tecnologies CMOS estàndard. En concret, els detectors de GAPDs fan possible la conversió directa d’un esdeveniment generat per una sola partícula en un senyal CMOS digital amb un temps inferior al nanosegon. Com a resultat d’aquest fet, els GAPDs poden ser llegits després de cada bunch crossing (la col•lisió de les partícules), una qualitat única que cap dels seus competidors pot oferir en el moment actual. Malgrat tots aquests avantatges, els detectors de GAPDs pateixen dos grans problemes. D’una banda, existeixen fenòmens de soroll inherents al sensor, els quals indueixen polsos de soroll que no poden ser distingits dels esdeveniments reals generats per partícules i que a més empitjoren l’ocupació del detector a nivells inacceptables. D’altra banda, el fill-factor (és a dir, l’àrea sensible respecte l’àrea total) és molt baix i redueix l’eficiència detectora. En aquesta tesi s’han investigat solucions als dos problemes comentats i que a més compleixen amb les especificacions altament severes dels futurs col•lisionadors lineals. El detector de píxels de GAPDs, el qual ha estat monolíticament integrat en un procés HV-CMOS estàndard de 0.35 μm, incorpora circuits de lectura en mode voltatge que permeten operar el sensor en l’anomenat mode time-gated per tal de reduir el soroll detectat. L’eficiència de la tècnica proposada queda demostrada amb la gran varietat d’experiments que s’han dut a terme. Els resultats del beam-test dut a terme al CERN indiquen la capacitat del detector de píxels de GAPDs per detectar partícules altament energètiques. A banda d’això, també s’han estudiat els beneficis d’integrar un detector de píxels de GAPDs en un procés 3D per tal d’incrementar el fill-factor. L’anàlisi realitzat conclou que es poden assolir fill-factors superiors al 90%