Enhanced-accuracy oversampled data converters

Digital-to-analog converters (DACs) suffer from static and dynamic nonlinearity problems, which degrade their accuracy and performance. Mismatch errors in the analog components restrict the maximum achievable linearity. This thesis presents various techniques for correcting these errors. It describes a correction process for the nonlinear behavior of DACs, on three different levels: architectural design, circuit design, and layout design. The main results achieved are listed below: • Novel topologies using stochastic approaches to linearize multibit converters are presented. • A new method is introduced for avoiding the use of multibit DACs in the main loop of multi-path DS analog-to-digital converters (ADCs), which, combined with a novel noise leakage compensation technique, allows the use of low quality inner DACs. • A novel correction algorithm is proposed, which is based on the acquisition of the individual DAC errors by means of correlation procedures. The extracted values are used for correction purposes. The technique is capable of background operation. • Different circuits are proposed to improve the performance of current-steering DACs. Also, novel layout techniques are shown for reducing the spatial variations of the unit sources. Some of the presented techniques were combined in a prototype chip, designed and fabricated in a 0.35μm CMOS process. Simulation and preliminary measurement results show that they are effective.Keywords: data converters, digital-to-analog, integrated circuits, analog-to-digital, CMO

A survey on continuous-time modulators : theory, designs and implementations

Recently, delta-sigma modulation has become a widely applied technique for high-performance analog-to-digital conversion of narrow-band signals. Most of the early designs used discrete-time structure for good accuracy and good linearity. The transfer functions are independent of the clock frequency. However, high unity-gain bandwidths of the opamps are required to satisfy the settling accuracy required in the discrete-time designs. Continuous-time structure can potentially achieve higher clock frequency with less power consumption. the anti-aliasing filter can also be eliminated due to the anti-aliasing property of CT modulators. On the other hand, CT ADC have their own problems, such as jitter sensitivity and excess loop delay. In this thesis, the state-of-the-art of CT modulator is reviewed. The problems in the design of CT ADCs are analyzed and solutions to them are described. The theory, design and implementations of CT modulator will also be reviewed.Keywords: Continuous-Time, Delta-Sigm

Layout-accurate Ultra-fast System-level Design Exploration Through Verilog-ams

This research addresses problems in designing analog and mixed-signal (AMS) systems by bridging the gap between system-level and circuit-level simulation by making simulations fast like system-level and accurate like circuit-level. The tools proposed include metamodel integrated Verilog-AMS based design exploration flows. The research involves design centering, metamodel generation flows for creating efficient behavioral models, and Verilog-AMS integration techniques for model realization. The core of the proposed solution is transistor-level and layout-level metamodeling and their incorporation in Verilog-AMS. Metamodeling is used to construct efficient and layout-accurate surrogate models for AMS system building blocks. Verilog-AMS, an AMS hardware description language, is employed to build surrogate model implementations that can be simulated with industrial standard simulators. The case-study circuits and systems include an operational amplifier (OP-AMP), a voltage-controlled oscillator (VCO), a charge-pump phase-locked loop (PLL), and a continuous-time delta-sigma modulator (DSM). The minimum and maximum error rates of the proposed OP-AMP model are 0.11 % and 2.86 %, respectively. The error rates for the PLL lock time and power estimation are 0.7 % and 3.0 %, respectively. The OP-AMP optimization using the proposed approach is ~17000× faster than the transistor-level model based approach. The optimization achieves a ~4× power reduction for the OP-AMP design. The PLL parasitic-aware optimization achieves a 10× speedup and a 147 µW power reduction. Thus the experimental results validate the effectiveness of the proposed solution

Improved design techniques for low-voltage low-power switched-capacitor delta-sigma modulators

This dissertation investigates the constraints which arise when switched-capacitor (SC) delta-sigma modulators are designed for low-voltage operation, targeting also low power dissipation, and proposes methods of improving the performance and optimizing for low power dissipation. This is accomplished by identifying critical elements whose performance can lead to increased power dissipation, as well as the fundamental limitations of available analog circuit techniques. A prototype was designed and fabricated, which reflected these findings, and therefore exhibited good performance and nearly optimum power dissipation. One of the key performance parameters is the dc gain of the amplifier in the first stage; it should be high. This is necessary for high linearity and low quantization noise leakage. In low-voltage operation, it may become impractical to use conventional topologies employing cascoding techniques (e.g., folded-cascode) which provide high gain in one single stage. Rather, cascaded structures have to be used. The disadvantage of the latter is the necessity for frequency compensation which results in increased power dissipation. Hence, another objective of this work is to exploit techniques which compensate for the open-loop gain characteristic of the amplifier (dc gain and nonlinearity), thus permitting the utilization of single-stage low-gain topologies. Predictive correlated double sampling is one of such techniques and is analyzed in detail

High-Bandwidth Voltage-Controlled Oscillator based architectures for Analog-to-Digital Conversion

The purpose of this thesis is the proposal and implementation of data conversion open-loop architectures based on voltage-controlled oscillators (VCOs) built with ring oscillators (RO-based ADCs), suitable for highly digital designs, scalable to the newest complementary metal-oxide-semiconductor (CMOS) nodes. The scaling of the design technologies into the nanometer range imposes the reduction of the supply voltage towards small and power-efficient architectures, leading to lower voltage overhead of the transistors. Additionally, phenomena like a lower intrinsic gain, inherent noise, and parasitic effects (mismatch between devices and PVT variations) make the design of classic structures for ADCs more challenging. In recent years, time-encoded A/D conversion has gained relevant popularity due to the possibility of being implemented with mostly digital structures. Within this trend, VCOs designed with ring oscillator based topologies have emerged as promising candidates for the conception of new digitization techniques. RO-based data converters show excellent scalability and sensitivity, apart from some other desirable properties, such as inherent quantization noise shaping and implicit anti-aliasing filtering. However, their nonlinearity and the limited time delay achievable in a simple NOT gate drastically limits the resolution of the converter, especially if we focus on wide-band A/D conversion. This thesis proposes new ways to alleviate these issues. Firstly, circuit-based techniques to compensate for the nonlinearity of the ring oscillator are proposed and compared to equivalent state-of-the-art solutions. The proposals are designed and simulated in a 65-nm CMOS node for open-loop RO-based ADC architectures. One of the techniques is also validated experimentally through a prototype. Secondly, new ways to artificially increase the effective oscillation frequency are introduced and validated by simulations. Finally, new approaches to shape the quantization noise and filter the output spectrum of a RO-based ADC are proposed theoretically. In particular, a quadrature RO-based band-pass ADC and a power-efficient Nyquist A/D converter are proposed and validated by simulations. All the techniques proposed in this work are especially devoted for highbandwidth applications, such as Internet-of-Things (IoT) nodes or maximally digital radio receivers. Nevertheless, their field of application is not restricted to them, and could be extended to others like biomedical instrumentation or sensing.El propósito de esta tesis doctoral es la propuesta y la implementación de arquitecturas de conversión de datos basadas en osciladores en anillos, compatibles con diseños mayoritariamente digitales, escalables en los procesos CMOS de fabricación más modernos donde las estructuras digitales se ven favorecidas. La miniaturización de las tecnologías CMOS de diseño lleva consigo la reducción de la tensión de alimentación para el desarrollo de arquitecturas pequeñas y eficientes en potencia. Esto reduce significativamente la disponibilidad de tensión para saturar transistores, lo que añadido a una ganancia cada vez menor de los mismos, ruido y efectos parásitos como el “mismatch” y las variaciones de proceso, tensión y temperatura han llevado a que sea cada vez más complejo el diseño de estructuras analógicas eficientes. Durante los últimos años la conversión A/D basada en codificación temporal ha ganado gran popularidad dado que permite la implementación de estructuras mayoritariamente digitales. Como parte de esta evolución, los osciladores controlados por tensión diseñados con topologías de oscilador en anillo han surgido como un candidato prometedor para la concepción de nuevas técnicas de digitalización. Los convertidores de datos basados en osciladores en anillo son extremadamente sensibles (variación de frecuencia con respecto a la señal de entrada) así como escalables, además de otras propiedades muy atractivas, como el conformado espectral de ruido de cuantificación y el filtrado “anti-aliasing”. Sin embargo, su respuesta no lineal y el limitado tiempo de retraso alcanzable por una compuerta NOT restringen la resolución del conversor, especialmente para conversión A/D en aplicaciones de elevado ancho de banda. Esta tesis doctoral propone nuevas técnicas para aliviar este tipo de problemas. En primer lugar, se proponen técnicas basadas en circuito para compensar el efecto de la no linealidad en los osciladores en anillo, y se comparan con soluciones equivalentes ya publicadas. Las propuestas se diseñan y simulan en tecnología CMOS de 65 nm para arquitecturas en lazo abierto. Una de estas técnicas presentadas es también validada experimentalmente a través de un prototipo. En segundo lugar, se introducen y validan por simulación varias formas de incrementar artificialmente la frecuencia de oscilación efectiva. Para finalizar, se proponen teóricamente dos enfoques para configurar nuevas formas de conformación del ruido de cuantificación y filtrado del espectro de salida de los datos digitales. En particular, son propuestos y validados por simulación un ADC pasobanda en cuadratura de fase y un ADC de Nyquist de gran eficiencia en potencia. Todas las técnicas propuestas en este trabajo están destinadas especialmente para aplicaciones de alto ancho de banda, tales como módulos para el Internet de las cosas o receptores de radiofrecuencia mayoritariamente digitales. A pesar de ello, son extrapolables también a otros campos como el de la instrumentación biomédica o el de la medición de señales mediante sensores.Programa de Doctorado en Ingeniería Eléctrica, Electrónica y Automática por la Universidad Carlos III de MadridPresidente: Juan Pablo Alegre Pérez.- Secretario: Celia López Ongil.- Vocal: Fernando Cardes Garcí

PROCESS AWARE ANALOG-CENTRIC SINGLE LEAD ECG ACQUISITION AND CLASSIFICATION CMOS FRONTEND

The primary objective of this research work is the development of a low power single-lead ECG analog front-end (AFE) architecture which includes acquisition, digitization, process aware efficient gain and frequency control mechanism and a low complexity classifier for the detecting asystole, extreme bardycardia and tachycardia. Recent research on ECG recording systems focuses on the design of a compact single-lead wearable/portable devices with ultra-low-power consumption and in-built hardware for diagnosis and prognosis. Since, the amplitude of the ECG signal varies from hundreds of µV to a few mV, and has a bandwidth of DC to 250 Hz, conventional front-ends use an instrument amplifier followed by a programmable gain amplifier (PGA) to amplify the input ECG signal appropriately. This work presents an mixed signal ECG fronted with an ultra-low power two-stage capacitive-coupled signal conditioning circuit (or an AFE), providing programmable amplification along with tunable 2nd order high pass and lowpass filter characteristics. In the contemporary state-of-the-art ECG recording systems, the gain of the amplifier is controlled by external digital control pins which are in turn dynamically controlled through a DSP. Therefore, an efficient automatic gain control mechanism with minimal area overhead and consuming power in the order of nano watts only. The AGC turns the subsequent ADC on only after output of the PGA (or input of the ADC) reaches a level for which the ADC achieves maximum signal-to-noise-ratio (SNR), hence saving considerable startup power and avoiding the use of DSP. Further, in any practical filter design, the low pass cut-off frequency is prone to deviate from its nominal value across process and temperature variations. Therefore, post-fabrication calibration is essential, before the signal is fed to an ADC, to minimize this deviation, prevent signal degradation due to aliasing of higher frequencies into the bandwidth for classification of ECG signals, to switch to low resolution processing, hence saving power and enhances battery lifetime. Another short-coming noticed in the literature published so far is that the classification algorithm is implemented in digital domain, which turns out to be a power hungry approach. Moreover, Although analog domain implementations of QRS complexes detection schemes have been reported, they employ an external micro-controller to determine the threshold voltage. In this regard, finally a power-efficient low complexity CMOS fully analog classifier architecture and a heart rate estimator is added to the above scheme. It reduces the overall system power consumption by reducing the computational burden on the DSP. The complete proposed scheme consists of (i) an ultra-low power QRS complex detection circuit using an autonomous dynamic threshold voltage, hence discarding the need of any external microcontroller/DSP and calibration (ii) a power efficient analog classifier for the detection of three critical alarm types viz. asystole, extreme bradycardia and tachycardia. Additionally, a heart rate estimator that provides the number of QRS complexes within a period of one minute for cardiac rhythm (CR) and heart rate variability (HRV) analysis. The complete proposed architecture is implemented in UMC 0.18 µm CMOS technology with 1.8 V supply. The functionality of each of the individual blocks are successfully validated using postextraction process corner simulations and through real ECG test signals taken from the PhysioNet database. The capacitive feedback amplifier, Σ∆ ADC, AGC and the AFT are fabricated, and the measurement results are discussed here. The analog classification scheme is successfully validated using embed NXP LPC1768 board, discrete peak detector prototype and FPGA software interfac