27 research outputs found
Recommended from our members
Analysis of Improved µ-Law Companding Technique for OFDM Systems
YesHigh Peak-to-Average-Power Ratio (PAPR) of transmitted signals is a common problem in broadband telecommunication systems using an orthogonal frequency division multiplexing (OFDM) modulation scheme, as it increases transmitter power consumption. In consumer applications where it impacts mobile terminal battery life and infrastructure running costs, this is a major factor in customer satisfaction. Companding techniques have been recently used to alleviate this high PAPR. In this paper, a companding scheme with an offset, amidst two nonlinear companding levels, is proposed to achieve better PAPR reduction while maintaining an acceptable bit error rate (BER) level, resulting in electronic products of higher power efficiency. Study cases have included the effect of companding on the OFDM signal with and without an offset. A novel closed-form approximation for the BER of the proposed companding scheme is also presented, and its accuracy is compared against simulation results. A method for choosing best companding parameters is presented based on contour plots. Practical emulation of a real time OFDM-based system has been implemented and evaluated using a Field Programmable Gate Array (FPGA)
Recommended from our members
Continuous-Time and Companding Digital Signal Processors Using Adaptivity and Asynchronous Techniques
The fully synchronous approach has been the norm for digital signal processors (DSPs) for many decades. Due to its simplicity, the classical DSP structure has been used in many applications. However, due to its rigid discrete-time operation, a classical DSP has limited efficiency or inadequate resolution for some emerging applications, such as processing of multimedia and biological signals. This thesis proposes fundamentally new approaches to designing DSPs, which are different from the classical scheme. The defining characteristic of all new DSPs examined in this thesis is the notion of "adaptivity" or "adaptability." Adaptive DSPs dynamically change their behavior to adjust to some property of their input stream, for example the rate of change of the input. This thesis presents both enhancements to existing adaptive DSPs, as well as new adaptive DSPs. The main class of DSPs that are examined throughout the thesis are continuous-time (CT) DSPs. CT DSPs are clock-less and event-driven; they naturally adapt their activity and power consumption to the rate of their inputs. The absence of a clock also provides a complete avoidance of aliasing in the frequency domain, hence improved signal fidelity. The core of this thesis deals with the complete and systematic design of a truly general-purpose CT DSP. A scalable design methodology for CT DSPs is presented. This leads to the main contribution of this thesis, namely a new CT DSP chip. This chip is the first general-purpose CT DSP chip, able to process many different classes of CT and synchronous signals. The chip has the property of handling various types of signals, i.e. various different digital modulations, both synchronous and asynchronous, without requiring any reconfiguration; such property is presented for the first time CT DSPs and is impossible for classical DSPs. As opposed to previous CT DSPs, which were limited to using only one type of digital format, and whose design was hard to scale for different bandwidths and bit-widths, this chip has a formal, robust and scalable design, due to the systematic usage of asynchronous design techniques. The second contribution of this thesis is a complete methodology to design adaptive delay lines. In particular, it is shown how to make the granularity, i.e. the number of stages, adaptive in a real-time delay line. Adaptive granularity brings about a significant improvement in the line's power consumption, up to 70% as reported by simulations on two design examples. This enhancement can have a direct large power impact on any CT DSP, since a delay line consumes the majority of a CT DSP's power. The robust methodology presented in this thesis allows safe dynamic reconfiguration of the line's granularity, on-the-fly and according to the input traffic. As a final contribution, the thesis also examines two additional DSPs: one operating the CT domain and one using the companding technique. The former operates only on level-crossing samples; the proposed methodology shows a potential for high-quality outputs by using a complex interpolation function. Finally, a companding DSP is presented for MPEG audio. Companding DSPs adapt their dynamic range to the amplitude of their input; the resulting can offer high-quality outputs even for small inputs. By applying companding to MPEG DSPs, it is shown how the DSP distortion can be made almost inaudible, without requiring complex arithmetic hardware
Solutions pour l'auto-adaptation des systèmes sans fil
The current demand on ubiquitous connectivity imposes stringent requirements on the fabrication of Radio-Frequency (RF) circuits. Designs are consequently transferred to the most advanced CMOS technologies that were initially introduced to improve digital performance. In addition, as technology scales down, RF circuits are more and more susceptible to a lot of variations during their lifetime, as manufacturing process variability, temperature, environmental conditions, aging… As a result, the usual worst-case circuit design is leading to sub-optimal conditions, in terms of power and/or performance most of the time for the circuit. In order to counteract these variations, increasing the performances and also reduce power consumption, adaptation strategies must be put in place.More importantly, the fabrication process introduces more and more performance variability, which can have a dramatic impact on the fabrication yield. That is why RF designs are not easily fabricated in the most advanced CMOS technologies, as 32nm or 22nm nodes for instance. In this context, the performances of RF circuits need to be calibrated after fabrication so as to take these variations into account and recover yield loss.This thesis work is presenting on a post-fabrication calibration technique for RF circuits. This technique is performed during production testing with minimum extra cost, which is critical since the cost of test can be comparable to the cost of fabrication concerning RF circuits and cannot be further raised. Calibration is enabled by equipping the circuit with tuning knobs and sensors. Optimal tuning knob identification is achieved in one-shot based on a single test step that involves measuring the sensor outputs once. For this purpose, we rely on variation-aware sensors which provide measurements that remain invariant under tuning knob changes. As an auxiliary benefit, the variation-aware sensors are non-intrusive and totally transparent to the circuit.Our proposed methodology has first been demonstrated with simulation data with an RF power amplifier as a case study. Afterwards, a silicon demonstrator has then been fabricated in a 65nm technology in order to fully demonstrate the methodology. The fabricated dataset of circuits is extracted from typical and corner wafers. This feature is very important since corner circuits are the worst design cases and therefore the most difficult to calibrate. In our case, corner circuits represent more than the two third of the overall dataset and the calibration can still be proven. In details, fabrication yield based on 3 sigma performance specifications is increased from 21% to 93%. This is a major performance of the technique, knowing that worst case circuits are very rare in industrial fabrication.La demande courante de connectivité instantanée impose un cahier des charges très strict sur la fabrication des circuits Radio-Fréquences (RF). Les circuits doivent donc être transférées vers les technologies les plus avancées, initialement introduites pour augmenter les performances des circuits purement numériques. De plus, les circuits RF sont soumis à de plus en plus de variations et cette sensibilité s’accroît avec l’avancées des technologies. Ces variations sont par exemple les variations du procédé de fabrication, la température, l’environnement, le vieillissement… Par conséquent, la méthode classique de conception de circuits “pire-cas” conduit à une utilisation non-optimale du circuit dans la vaste majorité des conditions, en termes de performances et/ou de consommation. Ces variations doivent donc être compensées, en utilisant des techniques d’adaptation.De manière plus importante encore, le procédé de fabrication des circuits introduit de plus en plus de variabilité dans les performances des circuits, ce qui a un impact important sur le rendement de fabrication des circuits. Pour cette raison, les circuits RF sont difficilement fabriqués dans les technologies CMOS les plus avancées comme les nœuds 32nm ou 22nm. Dans ce contexte, les performances des circuits RF doivent êtres calibrées après fabrication pour prendre en compte ces variations et retrouver un haut rendement de fabrication.Ce travail de these présente une méthode de calibration post-fabrication pour les circuits RF. Cette méthodologie est appliquée pendant le test de production en ajoutant un minimum de coût, ce qui est un point essentiel car le coût du test est aujourd’hui déjà comparable au coût de fabrication d’un circuit RF et ne peut être augmenté d’avantage. Par ailleurs, la puissance consommée est aussi prise en compte pour que l’impact de la calibration sur la consommation soit minimisé. La calibration est rendue possible en équipant le circuit avec des nœuds de réglages et des capteurs. L’identification de la valeur de réglage optimale du circuit est obtenue en un seul coup, en testant les performances RF une seule et unique fois. Cela est possible grâce à l’utilisation de capteurs de variations du procédé de fabrication qui sont invariants par rapport aux changements des nœuds de réglage. Un autre benefice de l’utilisation de ces capteurs de variation sont non-intrusifs et donc totalement transparents pour le circuit sous test. La technique de calibration a été démontrée sur un amplificateur de puissance RF utilisé comme cas d’étude. Une première preuve de concept est développée en utilisant des résultats de simulation.Un démonstrateur en silicium a ensuite été fabriqué en technologie 65nm pour entièrement démontrer le concept de calibration. L’ensemble des puces fabriquées a été extrait de trois types de wafer différents, avec des transistors aux performances lentes, typiques et rapides. Cette caractéristique est très importante car elle nous permet de considérer des cas de procédé de fabrication extrêmes qui sont les plus difficiles à calibrer. Dans notre cas, ces circuits représentent plus des deux tiers des puces à disposition et nous pouvons quand même prouver notre concept de calibration. Dans le détails, le rendement de fabrication passe de 21% avant calibration à plus de 93% après avoir appliqué notre méthodologie. Cela constitue une performance majeure de notre méthodologie car les circuits extrêmes sont très rares dans une fabrication industrielle
Enabling low cost test and tuning of difficult-to-measure device specifications: application to DC-DC converters and high speed devices
Low-cost test and tuning methods for difficult-to-measure specifications are presented in this research from the following perspectives: 1)"Safe" test and self-tuning for power converters: To avoid the risk of device under test (DUT) damage during conventional load/line regulation measurement on power converter, a "safe" alternate test structure is developed where the power converter (boost/buck converter) is placed in a different mode of operation during alternative test (light switching load) as opposed to standard test (heavy switching load) to prevent damage to the DUT during manufacturing test. Based on the alternative test structure, self-tuning methods for both boost and buck converters are also developed in this thesis. In addition, to make these test structures suitable for on-chip built-in self-test (BIST) application, a special sensing circuit has been designed and implemented. Stability analysis filters and appropriate models are also implemented to predict the DUT’s electrical stability condition during test and to further predict the values of tuning knobs needed for the tuning process. 2) High bandwidth RF signal generation: Up-convertion has been widely used in high frequency RF signal generation but mixer nonlinearity results in signal distortion that is difficult to eliminate with such methods. To address this problem, a framework for low-cost high-fidelity wideband RF signal generation is developed in this thesis. Depending on the band-limited target waveform, the input data for two interleaved DACs (digital-to-analog converters) system is optimized by a matrix-model-based algorithm in such a way that it minimizes the distortion between one of its image replicas in the frequency domain and the target RF waveform within a specified signal bandwidth. The approach is used to demonstrate how interferers with specified frequency characteristics can be synthesized at low cost for interference testing of RF communications systems. The frameworks presented in this thesis have a significant impact in enabling low-cost test and tuning of difficult-to-measure device specifications for power converter and high-speed devices.Ph.D
Recommended from our members
Efficient Low Power Headphone Driver
In recent years, the consumer electronics market for battery-powered devices such as smartphones and tablets has been rapidly expanding. The requirements for audio CODEC in these portable devices have extended from merely supporting voice calls to high-fidelity music playback. As a result, audio driver performance has become one of the most important differentiating factors among products from different suppliers. There are three basic performance metrics that are typically used to benchmark audio modules: the maximum delivered output power, the audio fidelity measured in terms of dynamic range, THD+N, and finally the battery life. Maximizing all three of these performance metrics has proven to be an exceptionally hard task as portrayed by the research publications.This work presents an attempt to push all three of these metrics together and provide an acceptable balance which is achieved by selecting the right topology. Conventionally, headphone drivers are designed using a linear amplifier topology for many reasons- most prominently- to achieve a superior THD+N and PSRR requirement which in the past was essentially the only key performance metric needed. This came at the expense of realizing mediocre power efficiency targets, thereby wasting battery life. This picture changed dramatically over the last decade with smartphones and other portable devices becoming the first choice of the young generation. These devices are extremely power hungry due to the unlimited functions and features they provide and therefore battery life has come to the spotlight as a key resource that need to be preserved. As a result, in this work a headphone driver is based on a switching topology that is able to deliver more than 230mW of power (or equivalently 2Vrms) to a 16Ω load while achieving better than -98dB of THD+N , more than 108dB of SNR, and about 108dB PSRR while still maintaining a peak power efficiency of more than 84%
Recommended from our members
Design and Linearization of Energy Efficiency Power Amplifier in Nonlinear OFDM Transmitter for LTE-5G Applications. Simulation and measurements of energy efficiency power amplifier in the presence of nonlinear OFDM transmitter system and digital predistortion based on Hammerstein-Wiener method
This research work has made an effort to understand a novel line of radio frequency
power amplifiers (RFPAs) that address initiatives for efficiency enhancement and
linearity compensation to harmonize the fifth generation (5G) campaign. The objective
is to enhance the performance of an orthogonal frequency division multiplexing-long
term evolution (OFDM-LTE) transmitter by reducing the nonlinear distortion of the
RFPA.
The first part of this work explores the design and implementation of 15.5 W class AB
RF power amplifier, adopting a balanced technique to stimulate efficiency enhancement
and redeeming exhibition of excessive power in the transmitter. Consequently, this work
goes beyond improving efficiency over a linear RF power amplifier design; in which a
comprehensive investigation on the fundamental and harmonic components of class F
RF power amplifier using a load-pull approach to realise an optimum load impedance
and the matching network is presented. The frequency bandwidth for both amplifiers was
allocated to operate in the 2.620-2.690 GHz of mobile LTE applications.
The second part explores the development of the behavioural model for the class AB
power amplifier. A particular novel, Hammerstein-Wiener based model is proposed to
describe the dynamic nonlinear behaviour of the power amplifier. The RF power amplifier
nonlinear distortion is approximated using a new linear parameter approximation
approach. The first and second-order Hammerstein-Wiener using the Normalised Least
Mean Square Error (NLMSE) algorithm is used with the aim of easing the complexity of
filtering process during linear memory cancellation. Moreover, an enhanced adaptive
Wiener model is proposed to explore the nonlinear memory effect in the system. The
proposed approach is able to balance between convergence speed and high-level
accuracy when compared with behavioural modelling algorithms that are more complex
in computation.
Finally, the adaptive predistorter technique is implemented and verified in the OFDM
transceiver test-bed. The results were compared against the computed one from
MATLAB simulation for OFDM and 5G modulation transmitters. The results have
confirmed the reliability of the model and the effectiveness of the proposed predistorter.FundacĂŁo para a CiĂŞncia e a Tecnologia, Portugal, under
European Union’s Horizon 2020 research and innovation programme ... grant agreement H2020-MSCA-ITN- 2016 SECRET-722424
I also acknowledge the role of the National Space Research and Development Agency (NASRDA)
Sokoto State Government
Petroleum Technology Trust Fund (PTDF
Proceedings of the Second International Mobile Satellite Conference (IMSC 1990)
Presented here are the proceedings of the Second International Mobile Satellite Conference (IMSC), held June 17-20, 1990 in Ottawa, Canada. Topics covered include future mobile satellite communications concepts, aeronautical applications, modulation and coding, propagation and experimental systems, mobile terminal equipment, network architecture and control, regulatory and policy considerations, vehicle antennas, and speech compression