EACOF: A Framework for Providing Energy Transparency to enable Energy-Aware Software Development

Making energy consumption data accessible to software developers is an essential step towards energy efficient software engineering. The presence of various different, bespoke and incompatible, methods of instrumentation to obtain energy readings is currently limiting the widespread use of energy data in software development. This paper presents EACOF, a modular Energy-Aware Computing Framework that provides a layer of abstraction between sources of energy data and the applications that exploit them. EACOF replaces platform specific instrumentation through two APIs - one accepts input to the framework while the other provides access to application software. This allows developers to profile their code for energy consumption in an easy and portable manner using simple API calls. We outline the design of our framework and provide details of the API functionality. In a use case, where we investigate the impact of data bit width on the energy consumption of various sorting algorithms, we demonstrate that the data obtained using EACOF provides interesting, sometimes counter-intuitive, insights. All the code is available online under an open source license. http://github.com/eaco

Valgreen: an Application's Energy Profiler

International audienceThe popularity of hand-held and portable devices put the energy aware computing in evidence. The need for long time batteries surpasses the hardware manufacturer, impacting the operational system policies and software development. Power modeling of applications has been studied during the last years and can be used to estimate their total energy. In order to aid the programmer to implement energy efficient algorithms, this paper introduces an application's energy profiler, namely Valgreen, which exploits the battery's information in order to generate an architecture independent power model through a calibration process

A Multi-start Local Search Scheduler for an Energy-aware Cloud Manager

International audienceThe field of cloud computing uses different management techniques for data center virtualization such as OpenNebula. However, computers composing the cloud infrastructure use a significant and growing portion of energy in the world specifically when dealing with virtualization for high performance computing (HPC). Therefore, energy-aware computing is crucial for large-scale systems that consume considerable amount of energy. In this paper, we present a new work that aims to deal with the energy consumption within a realistic cloud infrastructure using OpenNebula as a software management solution. Our scheduler is based on a multi-start local search heuristic that helps to find the best scheduling by dispatching the arriving of virtual machines (VM) according to the minimum energy consumption

DC:Small: Energy-aware Coordinated Caching in Cluster-based Storage Systems

As the computing capacity increases rapidly in large-scale cluster computing platforms, power management becomes an increasingly important concern. This project focuses on the research of reducing disk and memory power consumption through energy-aware cooperative caching in cluster-based storage systems. The project leverages I/O characteristics of scientific applications and dynamic power management features of disk drives and memory chips to reduce I/O energy consumption. This project involves three components: (1) investigate program context based pattern detection to predict I/O activities in the operating systems, (2) investigate disk energy aware cooperative cache management schemes, and (3) prototype the management schemes and incorporate into cluster-based file systems. This project has broader impact through its contributions to the energy-aware computing, graduate education, and undergraduate education via an existing NSF-REU site award

Energy-Aware Computing via Adaptive Precision under Performance Constraints in OFDM Wireless Receivers

International audienceTo cope with rapid variations of channel parameters , wireless receivers are designed with a significant performance margin to reach a given Bit Error Rate (BER), even for the worst-case channel conditions. Indeed, one of the steps during the design phase is the choice of the architecture bit-width, and the smallest wordlength that ensures the correct behaviour of the receiver is usually chosen. In this paper, an adaptive precision OFDM receiver is proposed. Significant energy savings come from varying at run time processing bit-width, based on estimation of channel conditions, without compromising the BER constraints. To validate the energy savings, the energy consumption of basic operators has been obtained from real measurements for different bit-widths on a FPGA and a processor using soft SIMD. Results show that up to 63% of the dynamic energy consumption can be saved using this adaptive technique

Experimental Evidence of Power Efficiency due to Architecture in Cellular Processor Array Chips

Speeding up algorithm execution can be achieved by increasing the number of processing cores working in parallel. Of course, this speedup is limited by the degree to which the algorithm can be parallelized. Equivalently, by lowering the operating frequency of the elementary processors, the algorithm can be realized in the same amount of time but with measurable power savings. An additional result of parallelization is that using a larger number of processors results in a more efficient implementation in terms of GOPS/W. We have found experimental evidence for this in the study of massively parallel array processors, mainly dedicated to image processing. Their distributed architecture reduces the energy overhead dedicated to data handling, thus resulting in a power efficient implementationMinisterio de Economía y Competitividad TEC2015-66878-C3-1-RCentro para el Desarrollo Tecnológico e Industrial IPC- 20111009Junta de Andalucía TIC 2338-2013Office of Naval Research (USA) N00014141035

Experimental Evidence of Power Efficiency due to Architecture in Cellular Processor Array Chips

Speeding up algorithm execution can be achieved by increasing the number of processing cores working in parallel. Of course, this speedup is limited by the degree to which the algorithm can be parallelized. Equivalently, by lowering the operating frequency of the elementary processors, the algorithm can be realized in the same amount of time but with measurable power savings. An additional result of parallelization is that using a larger number of processors results in a more efficient implementation in terms of GOPS/W. We have found experimental evidence for this in the study of massively parallel array processors, mainly dedicated to image processing. Their distributed architecture reduces the energy overhead dedicated to data handling, thus resulting in a power efficient implementationMinisterio de Economía y Competitividad TEC2015-66878-C3-1-RCentro para el Desarrollo Tecnológico e Industrial IPC- 20111009Junta de Andalucía TIC 2338-2013Office of Naval Research (USA) N00014141035

Online Estimation of Battery Lifetime for Wireless Sensors Network

Battery is a major hardware component of wireless sensor networks. Most of them have no power supply and are generally deployed for a long time. Researches have been done on battery physical model and their adaptation for sensors. We present an implementation on a real sensor operating system and how architectural constraints have been assumed. Experiments have been made in order to test the impact of some parameter, as the application throughput, on the battery lifetime