Magneto-ionic suppression of magnetic vortices

Magneto-ionics refers to the non-volatile control of the magnetic properties of materials by voltage-driven ion migration. This phenomenon constitutes one of the most important magnetoelectric mechanisms and, so far, it has been employed to modify the magnetic easy axis of thin films, their coercivity or their net magnetization. Herein, a novel magneto-ionic effect is demonstrated: the transition from vortex to coherent rotation states, caused by voltage-induced ion motion, in arrays of patterned nanopillars. Electrolyte-gated Co/GdOx bilayered nanopillars are chosen as a model system. Electron microscopy observations reveal that, upon voltage application, oxygen ions diffuse from GdOx to Co, resulting in the development of paramagnetic oxide phases (CoOx) along sporadic diffusion channels. This breaks up the initial magnetization configuration of the ferromagnetic pillars (i.e. vortex states) and leads to the formation of small ferromagnetic nanoclusters, embedded in the CoOx matrix, which behave as single-domain nanoparticles. As a result, a decrease in the net magnetic moment is observed, together with a drastic change in the shape of the hysteresis loop. Micromagnetic simulations are used to interpret these findings. These results pave the way towards a new potential application of magnetoelectricity: the magneto-ionic control of magnetic vortex states

Carbon nano-relays for low power switching

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 2009.Cataloged from PDF version of thesis.Includes bibliographical references (p. 147-153).In this thesis two unique carbon based nanoelectromechanical switches or carbon nano-relays are demonstrated as a toolkit for investigating NEMs based low power switching. The first is a vertical carbon nano-relay, consisting of a vertically aligned carbon nanotube/fiber (CN) between two contacts and operated by pull-off, and the second, a double graphene switch, consisting of two electromechanically actuated stacked layers of polycrystalline graphene. Vertical carbon nano-relays were initially prototyped by inserting a CN between two contacts through the use of a nanopositioner. The prototype demonstrated pull-off operation and multiple switching. To our knowledge this is the only example to date of a multiple-use NEMs switch that operates with pull-off. Next a wafer integrated device was fabricated. Although pull-in was demonstrated in these integrated devices, pull-off was not possible primarily due to limitations in CN growth, which were also investigated. In the work on a double graphene switch we demonstrated an electromechanical switch comprising two polycrystalline graphene films, each deposited using ambient pressure chemical vapor deposition (CVD). The top film is pulled into electrical contact with the bottom film by application of approximately 5V between the layers. Contact is broken by mechanical restoring forces after bias is removed. The device switches several times before tearing. Demonstration of multiple switching at low voltage confirms that graphene is an attractive material for electromechanical switches.by Kaveh Mehdi Milaninia.Ph.D

DEVELOPMENT OF NEMS RELAYS IN LOGIC COMPUTATION AND RUGGED ELECTRONICS

Ph.DDOCTOR OF PHILOSOPH

금속산화물 기반 저항변화메모리 소자의 노이즈 특성과 그것의 응용에 관한 연구

학위논문(박사) -- 서울대학교대학원 : 공과대학 전기·컴퓨터공학부, 2023. 2. 김재준.In the current pyramid-like structures memory hierarchy, it consists of, from top to bottom, a processing core, cache memory by static random access memory (SRAM), main memory by dynamic random access memory (DRAM), and storage memory by solid-state disk (SSD), or hard disk drive (HDD). In general, the closer to the processing core, the more high-speed operation is required, whereas the farther away from the core, the higher storage capacity is demanded. Consequently, the performance gap between DRAM and NAND Flash memory, which are currently major memory technologies, is continuously increasing. However, the need for new memory technology is increasing in order to solve the problem of data processing speed due to the explosive increase in the amount of data and the physical limitation of the existing memory technologies that has been raised for a long time. In addition, research and development on the storage class memory (SCM) technology is in progress as method of implementing In-Memory Process, a concept to solve the problem of Von Neumann architecture in various research groups. Among the candidates on the SCM, which satisfies both the high speed of DRAM and the density of NAND Flash, the resistive switching random access memory (RRAM) has been widely investigated as a leading candidate for next generation nonvolatile memory applications due to RRAMs advantageous features such as simple structure, low cost, high density, fast operation, and CMOS compatibility. However, the reliability issues which PCM suffered from is also being reproduced in RRAM. RRAMs various issues such as endurance, retention, and uniformity stem from intrinsic variability because resistive switching mechanism of RRAM itself is fundamentally stochastic. The main content of this dissertation is to develop a new electrical analysis technique to improve the reliability of RRAM. First, the elementary low frequency noise (LFN) characteristics of various RRAM devices were analyzed, and the correlation between LFN characteristics and the conduction/resistive switching mechanisms was experimentally verified. Also, it was suggested that the LFN measurement can be an additional analysis technique for devices degradation mechanism and multi-level cell (MLC) operation. Finally, from the random telegraph noise (RTN) measurement, we conducted a study to extract the position and energy of traps that can cause cells failure. The experiment on the extraction of traps physical information using the RTN measurement was conducted for the first in this study, and then research findings provided researchers with guidelines for the RTN analysis of RRAM.현재의 메모리 계층도를 보면 CPU는 고속 동작을 요구하고, 외부메모리는 고용량을 필요로 하기 때문에, 현재의 주요 메모리 기술인 DRAM과 NAND Flash 메모리의 성능 격차는 지속적으로 늘어나고 있다. 하지만 데이터 양의 폭발적인 증가로 인한 데이터 처리 속도 문제, 그리고 오래전부터 제기 되어왔던 기존 메모리의 물리적 한계를 해결하기 위해서 새로운 메모리 기술에 대한 필요성이 증가하고 있다. 또한 기존 폰노이만방식의 컴퓨터 시스템 구조의 문제점을 해결하기 위한 방법인 In-Memory Process를 실현하기 위한 방법으로 DRAM의 high speed, 그리고 NAND Flash의 high density 모두를 만족하는 SCM (storage class memory)기술에 대한 관심이 증가하고 있다. SCM 후보군 중에서, 저항 변화 메모리 소자인 RRAM (Resistive Random Access Memory)은 MIM, cross-point 형태의 간단한 구조를 가지며, 공정 상 집적도 향상에 유리하고, 사용되는 물질이 CMOS공정과 호환 가능하다. 이러한 장점들로 인해 기존 Flash 메모리 소자의 대안으로 학계에서 많은 연구가 진행 되어 왔지만, 한 단계 앞서 연구가 진행되었던 PCM (Phase change RAM)이 겪고 있는 신뢰성 문제가 RRAM에서도 재현되고 있다. RRAM의 신뢰성 문제는 RRAM의 저항 스위칭 메커니즘 자체가 근본적으로 확률적이기 때문에 본질적 변동성에서 기인하는 것이다. 본 논문의 주요 내용은 RRAM의 신뢰성 향상을 위해서 새로운 전기적 분석기법을 개발하는 것이다. 우선 다양한 메커니즘으로 동작하는 RRAM소자의 기본적인 저주파 잡음 특성을 분석하고, 이를 소자의 전도 메커니즘 및 저항 변화 메커니즘과의 연관성을 검증하였다. 측정결과를 기존 저주파 잡음 이론을 통해 해석하고, 다양한 소자에 이를 적용시켜 저주파 잡음 분석 기법이 RRAM의 동작 메커니즘 분석에 이용할 수 있음을 증명하였다. 또한, 소자의 열화 메커니즘 및 MLC (Multi-Level Cell) 분석에 있어서도 저주파 잡음 측정이 추가적인 분석기법이될 수 있음을 제시하였다. 마지막으로, 소자의 저주파 잡음 특성 중 하나인 RTN (Random Telegraph Noise)특성 분석을 통해 셀의 fail 을 일으킬 수 있는 trap의 위치 및 에너지를 추출하는 연구를 진행하였다. RRAM의 trap정보 추출에 관한 측정 및 분석은 본 연구에서 최초로 진행되었던 것이고, 이후 RRAM의 RTN분석에 가이드라인을 제시하였다.Chapter1 Introduction 1 1.1 Memory trends 1 1.1.1 Memory wall 1 1.1.2 In-memory processing 3 1.2 SCM technologies 4 1.2.1 Phase change memory 4 1.2.2 Magnetic memory 6 1.2.3 Ferroelectric memory 7 1.2.4 Resistive memory 8 1.3 Thesis content overview 12 1.3.1 Thesis objectives 12 1.3.2 Thesis outline 13 Chapter2 Overview on conduction mechanisms 14 2.1 Electrode-limited conduction mechanisms 14 2.1.1 Schottky emission 15 2.1.2 Fowler-Nordheim (F-N) and direct tunneling 17 2.2 Bulk-limited conduction mechanisms 18 2.2.1 Poole-Frenkel (P-F) emission 18 2.2.2 Ohmic conduction 19 2.2.3 Space charge limited conduction (SCLC) 20 Chapter3 LFN applications for RRAM analysis 23 3.1 Introduction to 1/f 23 3.2 LFN application (1): Resistive switching analysis 26 3.3 LFN application (2): MLC analysis 30 3.4 LFN application (3): Degradation analysis 35 Chapter4 Analysis of conduction mechanism using LFN 39 4.1 Thermochemical mechanism RRAM 39 4.1.1 Fabrication 39 4.1.2 Experimental results: RS and I-V characteristics 40 4.1.3 Experimental results: LFN characteristics 46 4.2 Valence change mechanism RRAM 50 4.2.1 Fabrication 50 4.2.2 Experimental results: RS and I-V characteristics 52 4.2.3 Experimental results: LFN characteristics 55 4.3 Comparative analysis of conduction mechanism 58 4.3.1 Fabrication 58 4.3.2 Experimental results: RS and I-V characteristics 61 4.3.3 Experimental results: LFN characteristics 63 Chapter5 Random telegraph noise (RTN) in RRAM 67 5.1 Introduction to RTN 67 5.2 RTN in RRAM 69 5.2.1 Methodology for extracting trap information 69 5.2.2 Experimental results 73 Chapter6 78 Conclusions 78박

Piezotronic devices and integrated systems

Novel technology which can provide new solutions and enable augmented capabilities to CMOS based technology is highly desired. Piezotronic nanodevices and integrated systems exhibit potential in achieving these application goals. By combining laser interference lithography and low temperature hydrothermal method, an effective approach for ordered growth of vertically aligned ZnO NWs array with high-throughput and low-cost at wafer-scale has been developed, without using catalyst and with a superior control over orientation, location/density and morphology of as-synthesized ZnO NWs. Beyond the materials synthesis, by utilizing the gating effect produced by the piezopotential in a ZnO NW under externally applied deformation, strain-gated transistors (SGTs) and universal logic operations such as NAND, NOR, XOR gates have been demonstrated for performing piezotronic logic operations for the first time. In addition, the first piezoelectrically-modulated resistive switching device based on piezotronic ZnO NWs has also been presented, through which the write/read access of the memory cell is programmed via electromechanical modulation and the logic levels of the strain applied on the memory cell can be recorded and read out for the first time. Furthermore, the first and by far the largest 3D array integration of vertical NW piezotronic transistors circuitry as active pixel-addressable pressure-sensor matrix for tactile imaging has been demonstrated, paving innovative routes towards industrial-scale integration of NW piezotronic devices for sensing, micro/nano-systems and human-electronics interfacing. The presented concepts and results in this thesis exhibit the potential for implementing novel nanoelectromechanical devices and integrating with MEMS/NEMS technology to achieve augmented functionalities to state-of-the-art CMOS technology such as active interfacing between machines and human/ambient as well as micro/nano-systems capable of intelligent and self-sufficient multi-dimensional operations.Ph.D

New Logic Synthesis As Nanotechnology Enabler (invited paper)

Nanoelectronics comprises a variety of devices whose electrical properties are more complex as compared to CMOS, thus enabling new computational paradigms. The potentially large space for innovation has to be explored in the search for technologies that can support large-scale and high- performance circuit design. Within this space, we analyze a set of emerging technologies characterized by a similar computational abstraction at the design level, i.e., a binary comparator or a majority voter. We demonstrate that new logic synthesis techniques, natively supporting this abstraction, are the technology enablers. We describe models and data-structures for logic design using emerging technologies and we show results of applying new synthesis algorithms and tools. We conclude that new logic synthesis methods are required to both evaluate emerging technologies and to achieve the best results in terms of area, power and performance

Carbon Based Nanoelectromechanical Resonators.

Owing to their light mass and high Young’s modulus, carbon nanotubes (CNTs) and graphene are promising candidates for nanoelectromechanical resonators capable of ultrasmall mass and force sensing. Unfortunately, the mass sensitivity of CNT resonators is impeded by the low quality factor (Q) caused by intrinsic losses. Therefore, one should minimize dissipations or seek an external way to enhance Q in order to overcome the fundamental limits. In this thesis, I first carried out a one-step direct transfer technique to fabricate pristine CNT nanoelectronic devices at ambient temperature. This process technique prevents unwanted contaminations, further reducing surface losses. Using this technique, CNT resonators was fabricated and a fully suspended CNT p-n diode with ideality factor equal to 1 was demonstrated as well. Subsequently, the frequency tuning mechanisms of CNT resonators were investigated in order to study their nonlinear dynamics. Downward frequency tuning caused by capacitive spring softening effect was demonstrated for the first time in CNT resonators adopting a dual-gate configuration. Leveraging the ability to modulate the spring constant, parametric amplification was demonstrated for Q enhancement in CNT resonators. Here, the simplest parametric amplification scheme was implemented by modulating the spring constant of CNTs at twice the resonance frequency through electrostatic gating. Consequently, at least 10 times Q enhancement was demonstrated and Q of 700 at room temperature was the highest record to date. Moreover, parametric amplification shows strong dependence on DC gate voltages, which is believed due to the difference of frequency tunability in different vibrational regimes. Graphene takes advantages over CNTs due to the availability of wafer-scale graphene films synthesized by chemical vapor deposition (CVD) method. Thus, I also examined graphene resonators fabricated from CVD graphene films. Ultra-high frequency (UHV) graphene resonators were demonstrated, and the Qs of graphene resonators are around 100. Future directions of graphene resonators include investigating the potential losses, exploring the origin of nonlinear damping, and demonstrating parametric amplification for Q enhancement.Ph.D.Electrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/91487/1/chungwu_1.pd