EnSuRe: Energy & Accuracy Aware Fault-tolerant Scheduling on Real-time Heterogeneous Systems

This paper proposes an energy efficient real-time scheduling strategy called EnSuRe, which (i) executes real-time tasks on low power consuming primary processors to enhance the system accuracy by maintaining the deadline and (ii) provides reliability against a fixed number of transient faults by selectively executing backup tasks on high power consuming backup processor. Simulation results reveal that EnSuRe consumes nearly 25% less energy, compared to existing techniques, while satisfying the fault tolerance requirements. EnSuRe is also able to achieve 75% system accuracy with 50% system utilisation. Further, the obtained simulation outcomes are validated on benchmark tasks via a fault injection framework on Xilinx ZYNQ APSoC heterogeneous dual core platform

A Practical Framework to Study Low-Power Scheduling Algorithms on Real-Time and Embedded Systems

With the advanced technology used to design VLSI (Very Large Scale Integration) circuits, low-power and energy-efficiency have played important roles for hardware and software implementation. Real-time scheduling is one of the fields that has attracted extensive attention to design low-power, embedded/real-time systems. The dynamic voltage scaling (DVS) and CPU shut-down are the two most popular techniques used to design the algorithms. In this paper, we firstly review the fundamental advances in the research of energy-efficient, real-time scheduling. Then, a unified framework with a real Intel PXA255 Xscale processor, namely real-energy, is designed, which can be used to measure the real performance of the algorithms. We conduct a case study to evaluate several classical algorithms by using the framework. The energy efficiency and the quantitative difference in their performance, as well as the practical issues found in the implementation of these algorithms are discussed. Our experiments show a gap between the theoretical and real results. Our framework not only gives researchers a tool to evaluate their system designs, but also helps them to bridge this gap in their future works

Review of CPU Energy-Aware Parallel Real-Time Scheduling

This is a review of journals in the area of using Energy-Aware/Energy efficient real-time systems of various tasks on different types of multi-core platforms (in this case, specifically DAG). The journals have discussed the milestones that have been achieved in the area of embedded systems and how their is need for energy efficient solutions to handle this advancement. These papers also include some of the first scheduling algorithms that take prioritizes energy awareness when it comes to both global scheduling and federated sch Three articles have been reviewed titled as follows: - 1) CPU Energy-Aware Parallel Real-Time Scheduling by Zhishan Guo and others 2) Energy-Efficient Real-Time Scheduling of DAG Tasks by Zhishan Guo, Ashikahmed Bhuiyan and other

An adaptive, utilization-based approach to schedule real-time tasks for ARM big. LITTLE architectures

ARM big.LITTLE architectures are spreading more and more in the mobile world thanks to their power-saving capabilities due to the use of two ISA-compatible islands, one focusing on energy efficiency and the other one on computational power. This architecture makes the problem of energy-aware task scheduling particularly challenging, due to the number of variables to take into account and the need for having lightweight mechanisms that can be readily computed in an operating system kernel scheduler. This paper presents a novel task scheduler for big.LITTLE platforms, combining the well-known Constant Bandwidth Server algorithm with a power-aware per-job migration policy. This achieves real-time adaptation of the CPU islands' frequencies based on the individual cores' overall utilization, as available in the scheduler thanks to the use of the resource reservation paradigm. Preliminary results obtained by simulations based on modifications to the open-source RTSim tool show that the proposed technique is able to achieve interesting performance/energy trade-offs

Distribution Systems Efficiency

This paper constructing a measurement system for determining the efficiency of the distributed system. This efficiency depends on many parameters like number of terminals, number of customers and kind of information, number of nodes, and number of messages. It is found that the efficiency depends strongly on number of messages sent or received inside the distributed system, as the number of messages increased the efficiency decreased. Keywords: distributed system, terminals, efficiency

Energy-Efficient Concurrency Control for Dynamic-Priority Real-Time Tasks with Abortable Critical Sections

In this paper, we are interested in energy-efficient concurrency control for real-time tasks on a non-ideal DVS processor. Based on well-known ceiling-based concurrency control protocols (such as priority ceiling protocol (PCP) and stack resource policy (SRP)), researchers have proposed energy-efficient approaches to mange concurrent accesses to shared resources so that the energy consumption can be reduced. However, ceiling-based protocols have a problem of ceiling blocking which imposes a great impact on the performance of real-time systems. In order to achieve sufficient performance, we propose a new protocol, called conditional abortable stack resource policy (CA-SRP), to resolve the ceiling blocking problem for dynamic-priority real-time tasks by incorporating a conditional abort rule into SRP. Based on the schedulability analysis of CA-SRP, we also propose a method, called dynamic speed assignment (DSA), to dynamically calculate and assign proper processor speeds for task execution so that the energy consumption can be reduced further. The capabilities of our proposed CA-SRP and DSA have been evaluated by a series of experiments, for which we have encouraging results

A dynamic power-aware partitioner with task migration for multicore embedded systems

Nowadays, a key design issue in embedded systems is how to reduce the power consumption, since batteries have a limited energy budget. For this purpose, several techniques such as Dynamic Voltage Scaling (DVS) or task migration can be used. DVS allows reducing power by selecting the optimal voltage supply, while task migration achieves this effect by balancing the workload among cores. This paper first analyzes the impact on energy due to task migration in multicore embedded systems with DVS capability and using the well-known Worst Fit (WF) partitioning heuristic. To reduce overhead, migrations are only performed at the time that a task arrives to and/or leaves the system and, in such a case, only one migration is allowed. The huge potential on energy saving due to task migration, leads us to propose a new dynamic partitioner, namely DP, that migrates tasks in a more efficient way than typical partitioners. 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