Plasma Enhanced Chemical Vapor Deposition of Silicon Nitride and Oxynitride Films Using Disilane as Silicon Source.

Process characterization details along with the electrical properties of plasma enhanced chemical vapor deposited silicon nitride and oxynitride films are reported, for the first time, using disilane as the silicon source. Two regimes of deposition, namely excess-disilane regime and excess-ammonia regime, were observed for deposition of silicon nitride films using disilane, ammonia and helium. Films deposited under process conditions falling at the boundary of these two regimes had deposition rates that were mostly dependent on rf power and gas flow ratio resulting in highly repeatable film qualities. Silicon nitride films deposited on Si wafers at 250°C and post-metallization annealed in N2 ambient at 420°C exhibited fixed effective interface charge density of ∼3 x 1011 cm-2 and minimum interface state density of 2--3 x 1011cm -2 eV-1. The net bulk and interface charge density, charge trap density, interface trap density in the midbandgap region, and leakage current through the films were all lower for films that received a post-metallization anneal in both N2 and forming gas ambients compared to the values for films annealed in either N2 or forming gas ambients alone. All films exhibited higher instability due to hole trapping under negative gate bias stressing than due to electron trapping under positive gate bias stressing. Silicon oxynitride films were deposited by introducing N2O gas into the disilane/ammonia/helium gas system. Films deposited using higher N2O flow rates exhibited higher net effective fixed interface charge densities. The charge trapping in the films decreased with increasing N 2O flow rates employed in deposition except at the highest N2O flow rate investigated. In general, a turn-around behavior was observed in the trend for several electrical properties of the oxynitride films with increasing N2O flow rates. All the oxynitride films examined exhibited fewer occurrences of extrinsic breakdown compared to silicon nitride films, indicating reduction of pinhole density in the oxynitride films. Reviewing the overall properties of these films, it was deduced that the silicon oxynitride films deposited using NH3 to N2O flow rate of 20 in the present system would be the most practical choice for their use as gate dielectric films in thin film transistor applications

HfO2 as gate dielectric on Si and Ge substrate

Hafnium oxide HfO2 has been considered as an alternative to silicon dioxide SiO2 in future nano-scale complementary metal-oxide-semiconductor (CMOS) devices since it provides the required capacitance at the reduced device size because of its high dielectric constant. HfO2 films are currently deposited by various techniques. Many of them require high temperature annealing that can impact device performance and reliability. In this research, electrical characteristics of capacitors with HfO2 as gate dielectric deposited by standard thermal evaporation and e-beam evaporation on Si and Ge substrates were investigated. The dielectric constant of HfO2 deposited by thermal evaporation on Si is in the range of 18-25. Al/HfO2/Si MOS capacitors annealed at 450°C show low hysteresis, leakage current density and bulk oxide charges. Interface state density and low temperature charge trapping behavior of these structures were also investigated. Degradation in surface carrier mobility has been reported in Si field-effect-transistors with HfO2 as gate dielectric. To explore the possibility of alleviating this problem we have used germanium (Ge) substrate as this semiconductor has higher carrier mobility than Si. Devices fabricated by depositing HfO2 directly on Ge by standard thermal evaporation were found to be too leaky and show significant hysteresis and large shift in flatband voltage. This deterioration in electrical performance is mainly due to the formation of unstable interfacial layer of GeO2 during the HfO2 deposition. To minimize this effect, Ge surface was treated with the beam of atomic nitrogen prior to the dielectric deposition. The effect of surface nitridation, on interface as well as on bulk oxide, trap energy levels were investigated using low temperature C-V measurements. They revealed additional defect levels in the nitrided devices indicating diffusion of nitrogen from interface into the bulk oxide. Impact of surface nitridation on the reliability of Ge/HfO2/Al MOS capacitors has been investigated by application of constant voltage stress at different voltage levels for various time periods. It was observed that deeper trap levels in nitrided devices, found from low frequency and low temperature measurements, trap the charge carrier immediately after stress but with time these carriers detrap and create more traps inside the bulk oxide resulting in further devices deterioration. It is inferred that though nitrogen is effective in reducing interfacial layer growth it incorporates more defects at interface as well as in bulk oxide. Therefore, it is important to look into alternative methods of surface passivation to limit the growth of GeO2 at the interface

Process development and reliability of thin gate oxides

The Semiconductor Industry Association\u27s (SIA) current National Technological Roadmap calls for the development of a suitable dielectric material for use in gate oxide for the 0.18|micrometers generation of chips and beyond. Some of the key challenges identified are resistance to oxide trapped charge generation from higher levels of tunneling currents and/or plasma processing, and formation of an effective barrier to dopant penetration during the gate processing. One promising material to meet these challenges is nitrided thermal oxide. Development of a growth process that yields high quality, lOnm thick, thermally grown Si02 films at RJT for use as a gate dielectric is described. Thin oxides (8nm - 20nm) were grown by thermal oxidation followed by inert anneals in Ar and N2. Nitrided oxides were created by implanting N2 (dose range: 5el3 - lei 5 /cm2) into the substrate prior to gate oxidation. Test equipment was setup to study Fowler Nordheim (FN) tunneling and dielectric breakdown. Test structures consisted of conventional and novel MOS capacitor structures with aluminum and poly-silicon gate electrodes. Scaling RJT\u27s existing, 20nm oxidation process to lOnm resulted in degradation of dielectric strength from \u3e lOMV/cm to ~6-7MV/cm for Al-gate MOS capacitors. Replacing the Al gate material with poly-silicon restored the dielectric strength to lOMV/cm. Performing an N2 implant through a screening oxide, prior to gate oxidation, was investigated as a means of obtaining a nitrided thermal oxide. For certain doses (5el3 - 5el4 /cm2), Al-gate MOS capacitors exhibited an improved dielectric strength as the mean value increased from 6- 7MV/cm to ~9MV/cm. Poly-Si gate MOS capacitors showed a similar improvement for the nitrided oxides, exhibiting mean dielectric strength values in the 10-12MV/cm range. Fowler- Nordheim (FN) tunnel current measurements showed that the nitrided films exhibit lower leakage levels and less charge trapping than their thermal Si02 counterparts. Results indicate that a 12nm nitrided oxide, for a certain dose (5el4/cm2), exhibited equivalent electrical performance to a 20nm thermally grown Si02 oxide. In conclusion, a process was developed for yielding reliable thin gate oxides (~10nm) in a university fab

Germanium MOSFETs with high-K gate dielectric and advanced source/drain structure

Ph.DDOCTOR OF PHILOSOPH

Germanium MOS devices integrating high-k dielectric and metal gate

textThis dissertation investigates the fabrication and characteristics of the metaloxide-semiconductor (MOS) devices built on germanium substrates integrating HfO2 high-κ dielectric and TaN metal gate electrode. The metal-gate/high-κ/germanium MOS stack, by taking the advantages of the high carrier mobility from the germanium channel and the sub-nm equivalent-oxide-thickness (EOT) scaling capability from the high-κ dielectric and the metal gate electrode, offers a possible solution for the future advanced complementary MOS (CMOS) applications to further boast the transistors’ driving current for faster operation. Due to the unstable and poor-quality natively grown germanium oxide, surface treatment is very critical in germanium device fabrication in order to remove the native oxide and prevent its growth, as well as suppress the interdiffusion across the interface. Several wet cleaning methods and an in situ cleaning technique by Ar anneal have been investigated. Surface passivation techniques, including NH3-based surface nitridation (SN) by forming a GeOxNy layer and silicon interlayer (SiIL) passivation by growing an ultra-thin (several monolayer) silicon layer between the high-κ dielectric and the substrate, have been studied and proved able to improve device performance significantly. Both p- and n-channel germanium transistors have been successfully fabricated. 1.8X enhancement of peak mobility in p-channel and 2.5X in n-channel over the silicon control devices have been achieved. The interface growth mechanism between the germanium substrate and the dielectric layer has been investigated. Two competing processes occurring at the interface determine the formation of the interfacial layer and affect Ge outdiffusion. Substrate dopants are found playing important roles, which causes the variations in the interfacial layer formation on different types of substrates and so on in the electrical properties. The relatively high diffusivity of dopants and germanium atoms in bulk germanium and the induced structural defects near the surface may severely degrade the device performance. This can well explain the very poor performance of the n-channel devices reported recently by several groups. Performance degradation of the germanium devices after thermal anneal, which is resulting from the interdiffusion and germanium oxide desorption, suggests that thermal stability is a concern in high temperature processes and more stable passivation techniques may be required. Long term reliability study indicates that HfO2 dielectric with SN treatment on germanium is robust against TDDB stress and the long term reliability (TDDB) is not a concern for germanium MOS devices.Electrical and Computer Engineerin

Ultra-thin plasma nitrided oxide gate dielectrics for advanced MOS transistors

Ultra-thin plasma nitrided oxides have been optimized with the objective to decrease JG and maximize carrier mobility. It was found that while the base oxide cannot be aggressively scaled, plasma optimization yields better mobility thereby increase transistor performance. A summary of the EOT versus gate leakage current density of NMOS devices with plasma nitrided oxides is shown in Figure 5.19. EOT down to 1.2 nm has been achieved with a gate leakage current density of 40 A/cm2 at 1 V operating voltage

Reliability study of Zr and Al incorporated hf based high-k dielectric deposited by advanced processing

Hafnium-based high-x dielectric materials have been successfully used in the industry as a key replacement for SiO2 based gate dielectrics in order to continue CMOS device scaling to the 22-nm technology node. Further scaling according to the device roadmap requires the development of oxides with higher x values in order to scale the equivalent oxide thickness (EOT) to 0.7 nm or below while achieving low defect densities. In addition, next generation devices need to meet challenges like improved channel mobility, reduced gate leakage current, good control on threshold voltage, lower interface state density, and good reliability. In order to overcome these challenges, improvements of the high-x film properties and deposition methods are highly desirable. In this dissertation, a detail study of Zr and Al incorporated HfO2 based high-κ dielectrics is conducted to investigate improvement in electrical characteristics and reliability. To meet scaling requirements of the gate dielectric to sub 0.7 nm, Zr is added to HfO2 to form Hf1-xZrxO2 with x=0, 0.31 and 0.8 where the dielectric film is deposited by using various intermediate processing conditions, like (i) DADA: intermediate thermal annealing in a cyclical deposition process; (ii) DSDS: similar cyclical process with exposure to SPA Ar plasma; and (iii) As-Dep: the dielectric deposited without any intermediate step. MOSCAPs are formed with TiN metal gate and the reliability of these devices is investigated by subjecting them to a constant voltage stress in the gate injection mode. Stress induced flat-band voltage shift (ΔVFB), stress induced leakage current (SILC) and stress induced interface state degradation are observed. DSDS samples demonstrate the superior characteristics whereas the worst degradation is observed for DADA samples. Time dependent dielectric breakdown (TDDB) shows that DSDS Hf1-xZrxO2 (x=0.8) has the superior characteristics with reduced oxygen vacancy, which is affiliated to electron affinity variation in HfO2 and ZrO2. The trap activation energy levels estimated from the temperature dependent current voltage characteristics also support the observed reliability characteristics for these devices. In another experiment, HfO2 is lightly doped with Al with a variation in Al concentration by depositing intermediate HfAlOx layers. This work has demonstrated a high quality HfO2 based gate stack by depositing atomic layer deposited (ALD) HfAlOx along with HfO2 in a layered structure. In order to get multifold enhancement of the gate stack quality, both Al percentage and the distribution of Al are observed by varying the HfAlOx layer thickness and it is found that \u3c 2% Al/(Al+Hf)% incorporation can result in up to 18% reduction in the average EOT along with up to 41 % reduction in the gate leakage current as compared to the dielectric with no Al content. On the other hand, excess Al presence in the interfacial layer moderately increases the interface state density (Dit). When devices are stressed in the gate injection mode at a constant voltage stress, dielectrics with Al/(Hf+Al)% \u3c 2% show resistance to stress induced flat-band voltage shift (ΔVFB), and stress induced leakage current (SILC). The time dependent dielectric breakdown (TDDB) characteristics show a higher charge to breakdown and an increase in the extracted Weibull slope (β) that further confirms an enhanced dielectric reliability for devices with \u3c 2% Al/(Al+Hf)%

Chemical vapor deposition and characterization of polysilanes polymer based thin films and their applications in compound semiconductors and silicon devices

As the semiconductors industry is moving toward nanodevices, there is growing need to develop new materials and thin films deposition processes which could enable strict control of the atomic composition and structure of thin film materials in order to achieve precise control on their electrical and optical properties. The accurate control of thin film characteristics will become increasingly important as the miniaturization of semiconductor devices continue. There is no doubt that chemical synthesis of new materials and their self assembly will play a major role in the design and fabrication of next generation semiconductor devices. The objective of this work is to investigate the chemical vapor deposition (CVD) process of thin film using a polymeric precursor as a source material. This process offers many advantages including low deposition cost, hazard free working environment, and most importantly the ability to customize the polymer source material through polymer synthesis and polymer functionalization. The combination between polymer synthesis and CVD process will enable the design of new generation of complex thin film materials with a wide range of improved chemical, mechanical, electrical and optical properties which cannot be easily achieved through conventional CVD processes based on gases and small molecule precursors. In this thesis we mainly focused on polysilanes polymers and more specifically poly(dimethylsilanes). The interest in these polymers is motivated by their distinctive electronic and photonic properties which are attributed to the delocalization of the [sigma]-electron along the Si-Si backbone chain. These characteristics make polysilane polymers very promising in a broad range of applications as a dielectric, a semiconductor and a conductor. The polymer-based CVD process could be eventually extended to other polymer source materials such as polygermanes, as well as and a variety of other inorganic and hybrid organic-inorganic polymers. This work has demonstrated that a polysilane polymeric source can be used to deposit a wide range of thin film materials exhibiting similar properties with conventional ceramic materials such as silicon carbide (SiC), silicon oxynitride (SiON), silicon oxycarbide (SiOC) silicon dioxide (SiO[subscript 2]) and silicon nitride (Si[subscipt 3]N[subscript 4]). The strict control of the deposition process allows precise control of the electrical, optical and chemical properties of polymer-based thin films within a broad range. This work has also demonstrated for the first time that poly(dimethylsilmaes) polymers deposited by CVD can be used to effectively passivate both silicon and gallium arsenide MOS devices. This finding makes polymer-based thin films obtained by CVD very promising for the development of high-[kappa] dielectric materials for next generation high-mobility CMOS technology

Metal gate with high-K dielectric in Si CMOS processing

Ph.DDOCTOR OF PHILOSOPH

Hf-based high-K gate dielectric and metal gate stack for advanced CMOS devices

Ph.DDOCTOR OF PHILOSOPH