An adaptive true motion estimation algorithm for frame rate up-conversion and its hardware design

With the advancement in video and display technologies, recently flat panel High Definition Television (HDTV) displays with 100 Hz, 120 Hz and most recently 240 Hz picture rates are introduced. However, video materials are captured and broadcast in different temporal resolutions ranging from 24 Hz to 60 Hz. In order to display these video formats correctly on high picture rate displays, new frames should be generated and inserted into the original video sequence to increase its frame rate. Therefore, Frame Rate Up-Conversion (FRUC) has become a necessity. Motion Compensated FRUC algorithms provide better quality results than non-motion compensated FRUC algorithms. Motion Estimation (ME) is the process of finding motion vectors which describe the motion of the objects between adjacent frames and is the most computationally intensive part of motion compensated FRUC algorithms. For FRUC applications, it is important to find the motion vectors that represent real motions of the objects which is called true ME. In this thesis, an Adaptive True Motion Estimation (ATME) algorithm is proposed. ATME algorithm produces similar quality results with less number of calculations or better quality results with similar number of calculations compared to 3-D Recursive Search true ME algorithm by adaptively using optimized sets of candidate search locations and several redundancy removal techniques. In addition, 3 different complexity hardware architectures for ATME are proposed. The proposed hardware use efficient data re-use schemes for the non-regular data flow of ATME algorithm. 2 of these hardware architectures are implemented on Xilinx Virtex-4 FPGA and are capable of processing ~158 and ~168 720p HD frames per second respectively

Low power motion estimation based frame rate up-conversion hardware designs

Recently flat panel high definition television (HDTV) displays with 100 Hz, 120 Hz and 240 Hz picture rates are introduced. However, video materials are captured and broadcast in different temporal resolutions ranging from 24 Hz to 60 Hz. In order to display these video formats correctly on high picture rate displays, new frames should be generated and inserted into the original video sequence to increase its frame rate. Therefore, frame rate upconversion (FRUC) has become a necessity. Motion compensated FRUC (MC-FRUC) algorithms provide better quality results than non-motion compensated FRUC algorithms. These MC-FRUC algorithms consist of two main stages, motion estimation (ME) and motion compensated interpolation (MCI). In ME, motion vectors (MV) are calculated between successive frames, and in MCI this MV data is used to generate a new frame that is inserted between two successive frames, thus doubling the frame rate. In addition to these two main steps, intermediate steps such as refinement of the MV field by various algorithms like motion vector smoothing and bilateral ME refinement may be used to improve the quality of the interpolated video. In this thesis, a perfect absolute difference technique for block matching ME hardware is proposed. The proposed technique reduces the power consumption of a full search ME hardware by 2.2% on a XC2VP30-7 FPGA without any PSNR loss. In addition, a global motion estimation (GME) algorithm and its hardware implementation are proposed. The proposed GME algorithm increases PSNR of 3D recursive search ME algorithm by 2.5% and its hardware implementation is capable of processing 341 720p frames per second. An adaptive technique for GME, which reduces the energy consumption of the GME hardware by 14.37% on a XC6VLX75T FPGA with a 0.17% PSNR loss, is also proposed. Furthermore, an early termination technique for the adaptive bilateral motion estimation (ABIME) algorithm is proposed. The proposed technique reduces the energy consumption of the ABIME hardware by 29% with a 0.04% PSNR loss on a XC6VLX75T FPGA. In addition, an efficient weighted coefficient overlapped block motion compensation (WC-OBMC) hardware which reduces the dynamic power consumption of the reference WC-OBMC hardware by 22% is proposed. The proposed hardware is capable of processing 57 720p frames per second on a XC6VLX75T FPGA. Finally, the ABIME hardware is implemented on a Xilinx ML605 FPGA board

Proceedings of the Second International Mobile Satellite Conference (IMSC 1990)

Presented here are the proceedings of the Second International Mobile Satellite Conference (IMSC), held June 17-20, 1990 in Ottawa, Canada. Topics covered include future mobile satellite communications concepts, aeronautical applications, modulation and coding, propagation and experimental systems, mobile terminal equipment, network architecture and control, regulatory and policy considerations, vehicle antennas, and speech compression

Design and evaluation of OFDM radio interfaces for high mobility communications

[Resumo] Nas dúas últimas décadas, as modulacións multiportadora emerxeron como una solución de baixa complexidade para combatir os efectos do multitraxecto en comuniacións sen fíos. Entre elas, Orthogonal Frequency Division Multiplexing (OFOM) é posiblemente o esquema de modulación máis estudado, e tamén amplamente adoptado como alicerce de estándares da industria como WiMAX ou LTE. Sen embargo, OFDM é sensible a canles que varian ca tempo, unha característica dos escenarios con mobilidade, debido á aparición da interferencia entre portadoras (ICI). A implementación de equipamento hardware para o usuario final faise normalmente en chips dedicados, afnda que entornos de investigación, prefírense solucións máis flexibles. Unha aproximación popular é a coñecida como Software Defined Radio (SOR), onde os algoritmos de procesado de sinal se implementan en hardware reconfigurable como Digital Signal Processors (OSPs) e Field Programmable Gate Arrays (FPGAs). O obxectivo deste traballo é dobre. Por un lado, definir unha arquitectura para implementacións de tempo real de capas físicas basadas en OFDM usando como referencia O estándar WiMAX, probada Dunha plataforma composta por OSPs e FPGAs. Por outra banda, estudar os efectos da selectividade en tempo no sinal OFDM, definindo métodos de estimación de canle que teñen en conta a ICI, e evaluándoos tanto en simulación como con medidas experimentais. Seguíronse dúas aproximacións para caracterizar o comportamento de formas de onda OFDM baixo condicións de mobilidade, unha basada nun emulador de canle que traballa en tempo real, e outra en inducir grandes ensanchamentos Doppler no sinal mediante a extensión da duración do símbolo OFOM.[Resumen] En las dos últimas décadas, las modulaciones multiportadora han emergido como una solución de baja complejidad para combatir los efectos del multitrayecto en comunicaciones iDalámbricas. Entre ellas, Orthogonal Frequency Division Mulriplexing (OFDM) es posiblemente el esquema de modulación más estudiado, y también ampliamente adoptado como fundamento de estándares de la industria como WiMAX o LTE. Sin embargo, OFDM es sensible a canales que varían con el tiempo, una característica de los escenarios coo movilidad, debido a la aparicióo de la interferencia entre portadoras (ICI). La implementación de equipamiento hardware para el usuario final se hace normalmente en chips dedicados, aunque eo entornos de investigación, son preferibles soluciones más Hexibles. Una aproximación popular es la conocida como Software Defined Radio (SDR), donde los algOritmos de procesado de señal se implementan en hardware reconfigurable como Digital Signa! Processors (DSPs) y Field Programmable Gate AIrays (FPGAs). El objetivo de este trabajo es doble. Por un lado. definir una arquitectura para implementaciones de tiempo real de capas ¡lSicas basadas en OFDM usando como referencia el estándar WiMAX, probada en una plataforma compuesta por DSPs y FPGAs. Por otro lado, estudiar los efectos de la selectividad en tiempo en la señal OFDM, definiendo métodos de estimacióo de canal que tengan eo cueota la ICI, y evaluándolos tanto en simulación como con medidas experimenta1es. Se han seguido dos aproximaciones para caracterizar el comportamiento de formas de onda OFDM bajo condiciones de mobilidad, una basada en un emulador de canal que trabaja en tiempo real. y otra en inducir grandes ensanchamientos Doppler en la señal mediante la extensión de la duración del símbolo OFDM.[Abstract] In Ihe last two decades, multicarrier modulations have emerged as a low complexity solulion to combal the effects of Ihe multipalh in wireless communicalions. Among Ihem, Orthogonal Frequency Division Mulliplexing (OFOM) is possibly Ihe mosl sludied modulation scheme, and has a1so been widely adopted as Ihe foundation of induslry standards such as WiMAX or LTE. However, OFOM is sensitive lo time selective channels, which are featured in mobility scenarlos, due lO Ihe appearance of Inler-Carrier Interference (ICI). Implemenlation of hardware equipmenl for Ihe end user is usually implemenled in dedicaled chips, bul in researeh environments, more flexible solutions are preferred. One popular approach is the so ealled Software Defined Radio (SOR), where the signal processing a1gorithms are implemented in reconfigurable hardware sueh as Digital Signal Processors (DSPs) and Field Prograrnmable Gate Arrays (FPGAs). The aim of Ibis work is two-fold. On the one hand, to define an architeclure for Ihe implementation of real-time OFOM-based physical layers, using as a reference Ihe WiMAX standard, and it is tested on a platform composed by DSPs and FPGAs. On the olher hand, to study Ihe effeets of !he time seleetivity on !he OFOM signal, defining channel estimation me!hods aware of !he ICI, and ils evaluation bo!h in simulation as well as experimental measuremenls. Two approaches have been followed to assess the behavior of OFOM waveforms under mobility conditions, one based on a real-time channel emulator, and the other on inducing large Doppler spreads in !he signal by extending the duration of Ihe OFDM symbols

Novel source coding methods for optimising real time video codecs.

The quality of the decoded video is affected by errors occurring in the various layers of the protocol stack. In this thesis, disjoint errors occurring in different layers of the protocol stack are investigated with the primary objective of demonstrating the flexibility of the source coding layer. In the first part of the thesis, the errors occurring in the editing layer, due to the coexistence of different video standards in the broadcast market, are addressed. The problems investigated are ‘Field Reversal’ and ‘Mixed Pulldown’. Field Reversal is caused when the interlaced video fields are not shown in the same order as they were captured. This results in a shaky video display, as the fields are not displayed in chronological order. Additionally, Mixed Pulldown occurs when the video frame-rate is up-sampled and down-sampled, when digitised film material is being standardised to suit standard televisions. Novel image processing algorithms are proposed to solve these problems from the source coding layer. In the second part of the thesis, the errors occurring in the transmission layer due to data corruption are addressed. The usage of block level source error-resilient methods over bit level channel coding methods are investigated and improvements are suggested. The secondary objective of the thesis is to optimise the proposed algorithm’s architecture for real-time implementation, since the problems are of a commercial nature. The Field Reversal and Mixed Pulldown algorithms were tested in real time at MTV (Music Television) and are made available commercially through ‘Cerify’, a Linux-based media testing box manufactured by Tektronix Plc. The channel error-resilient algorithms were tested in a laboratory environment using Matlab and performance improvements are obtained