Skin-Effect Loss Models for Time- and Frequency-Domain PEEC Solver

published_or_final_versio

Reduced order models of integrated RF spiral inductors with geometrical and technological automatic parameterization

In this paper a method is presented for automatically generating a parameterized model of integrated inductors accounting for geometry and substrate effects. A multiparameter Krylov-subspace based moment matching method is used to reduce the three-dimensional integral equations describing the EM behavior of the inductor over the substrate. Parameterization enables optimization of geometry and substrate technology simultaneously

Entire domain basis function expansion of the differential surface admittance for efficient broadband characterization of lossy interconnects

This article presents a full-wave method to characterize lossy conductors in an interconnect setting. To this end, a novel and accurate differential surface admittance operator for cuboids based on entire domain basis functions is formulated. By combining this new operator with the augmented electric field integral equation, a comprehensive broadband characterization is obtained. Compared with the state of the art in differential surface admittance operator modeling, we prove the accuracy and improved speed of the novel formulation. Additional examples support these conclusions by comparing the results with commerical software tools and with measurements

Heterogeneous Integration of RF and Microwave Systems Using Multi-layer Low-Temperature Co-fired Ceramics Technology

[eng] The aim of this work is the development of a modelling methodology for the fast analysis of non-radiative multilayer RF passive components without compromising solution accuracy. Instead of following a compact model approach, oftenly used in integrated technologies, the method is based on a specialized quasi-static partial element equivalent circuit (PEEC) numerical solver. Besides speed and accuracy, the solver can be embedded in circuit simulators; thus, models are already available in the schematic entry. Using this framework, model scalability is enhanced in terms of geometry, substrate cross-section, material properties, topology and boundary conditions. The dissertation starts showing the actual performance of the obtained solver and the motivations beneath its development. Then, the description about solver development is splitted in three parts, but all of them are interrelated. First, the PEEC formulation is adapted according to relevant electromagnetic behaviour of the component. It is worth stressing that a different perspective related to the principle of virtual work is used in this formulation. The second part deals with the evaluation of partial elements, the core of the solver. It is carried out using analytical space-domain close-form solutions of the Green’s function (GF) of the substrate. Partial elements are then assembled into a mesh. Therefore, the importance of the mesh up on solution accuracy is discussed in the last part and a basic layout aware mesh generator is proposed. Practical application of the methodology includes the implementation of a library of RF passives for multilayer substrate. For validation, the chosen substrate is a low temperature co-fired ceramics (LTCC) technology. Different set of devices have been fabricated, characterized and compared against model prediction. In addition, the obtained results are also verified using state-of-the-art electromagnetic solvers.[spa] El objetivo de este trabajo es el desarrollo de una metodología de modelado para el análisis rápido, pero sin comprometer la precisión de la solución, de componentes pasivos no radiativos de RF en substratos multicapa. El método se basa en el algoritmo numérico cuasi-estático de los elementos parciales de circuito equivalente (PEEC). Éste puede ser incorporado en simuladores de circuitos; por tanto, los modelos ya están disponibles en la entrada de esquemático de forma transparente para el diseñador de circuitos. Utilizando este marco, la escalabilidad del modelo se mejora en términos de la geometría, la definición del corte tecnológico, las propiedades del material, la topología del componente y las condiciones de contorno electro-magnéticas. Esta disertación comienza mostrando las motivaciones que han llevado a su desarrollo y la capacidad real del método de resolución obtenido. A partir de aquí, se realiza la descripción de todo el desarrollo del marco numérico que se divide en tres partes que están interrelacionadas. En primer lugar, la formulación PEEC se adapta según el comportamiento electromagnético real del componente. Vale la pena subrayar que en esta formulación se utiliza una perspectiva diferente a la habitual y que está relacionada con el principio de los trabajos virtuales de d’Alembert. La segunda parte trata de cómo se evalúan los elementos parciales y constituye el núcleo principal del algoritmo. Se lleva a cabo utilizando soluciones analíticas de la función de Green (GF) del sustrato en el dominio espacial. Los elementos parciales, que forman la malla numérica del modelo, se ensamblan en la matriz del sistema siguiendo un procedimiento de análisis nodal modificado (MNA). En la última parte, se discute la importancia de la malla sobre la precisión de la solución y se propone un generador de malla basado en la física del componente y no sólo en la descripción de la geometría. Como aplicación práctica de la metodología, se realiza la generación de una biblioteca de componentes pasivos RF para sustratos multicapa

Constraint-Aware, Scalable, and Efficient Algorithms for Multi-Chip Power Module Layout Optimization

Moving towards an electrified world requires ultra high-density power converters. Electric vehicles, electrified aerospace, data centers, etc. are just a few fields among wide application areas of power electronic systems, where high-density power converters are essential. As a critical part of these power converters, power semiconductor modules and their layout optimization has been identified as a crucial step in achieving the maximum performance and density for wide bandgap technologies (i.e., GaN and SiC). New packaging technologies are also introduced to produce reliable and efficient multichip power module (MCPM) designs to push the current limits. The complexity of the emerging MCPM layouts is surpassing the capability of a manual, iterative design process to produce an optimum design with agile development requirements. An electronic design automation tool called PowerSynth has been introduced with ongoing research toward enhanced capabilities to speed up the optimized MCPM layout design process. This dissertation presents the PowerSynth progression timeline with the methodology updates and corresponding critical results compared to v1.1. The first released version (v1.1) of PowerSynth demonstrated the benefits of layout abstraction, and reduced-order modeling techniques to perform rapid optimization of the MCPM module compared to the traditional, manual, and iterative design approach. However, that version is limited by several key factors: layout representation technique, layout generation algorithms, iterative design-rule-checking (DRC), optimization algorithm candidates, etc. To address these limitations, and enhance PowerSynth’s capabilities, constraint-aware, scalable, and efficient algorithms have been developed and implemented. PowerSynth layout engine has evolved from v1.3 to v2.0 throughout the last five years to incorporate the algorithm updates and generate all 2D/2.5D/3D Manhattan layout solutions. These fundamental changes in the layout generation methodology have also called for updates in the performance modeling techniques and enabled exploring different optimization algorithms. The latest PowerSynth 2 architecture has been implemented to enable electro-thermo-mechanical and reliability optimization on 2D/2.5D/3D MCPM layouts, and set up a path toward cabinet-level optimization. PowerSynth v2.0 computer-aided design (CAD) flow has been hardware-validated through manufacturing and testing of an optimized novel 3D MCPM layout. The flow has shown significant speedup compared to the manual design flow with a comparable optimization result

System level power integrity transient analysis using a physics-based approach

With decreasing supply voltage level and massive demanding current on system chipset, power integrity design becomes more and more critical for system stability. The ultimate goal of well-designed power delivery network (PDN) is to deliver desired voltage level from the source to destination, in other words, to minimize voltage noise delivered to digital devices. The thesis is composed of three parts. The first part focuses on-die level power models including simplified chip power model (CPM) for system level analysis and the worst scenario current profile. The second part of this work introduces the physics-based equivalent circuit model to simplify the passive PDN model to RLC circuit netlist, to be compatible with any spice simulators and tremendously boost simulation speed. Then a novel system/chip level end-to-end transient model is proposed, including the die model and passive PDN model discussed in previous two chapters as well as a SIMPLIS based small signal VRM model. In the last part of the thesis, how to model voltage regulator module (VRM) is explicitly discussed. Different linear approximated VRM modeling approaches have been compared with the SIMPLIS small signal VRM model in both frequency domain and time domain. The comparison provides PI engineers a guideline to choose specific VRM model under specific circumstances. Finally yet importantly, a PDN optimization example was given. Other than previous PDN optimization approaches, a novel hybrid target impedance concept was proposed in this thesis, in order to improve system level PDN optimization process --Abstract, page iv

Fast methods for full-wave electromagnetic simulations of integrated circuit package modules

Fast methods for the electromagnetic simulation of integrated circuit (IC) package modules through model order reduction are demonstrated. The 3D integration of multiple functional IC chip/package modules on a single platform gives rise to geometrically complex structures with strong electromagnetic phenomena. This motivates our work on a fast full-wave solution for the analysis of such modules, thus contributing to the reduction in design cycle time without loss of accuracy. Traditionally, fast design approaches consider only approximate electromagnetic effects, giving rise to lumped-circuit models, and therefore may fail to accurately capture the signal integrity, power integrity, and electromagnetic interference effects. As part of this research, a second order frequency domain full-wave susceptance element equivalent circuit (SEEC) model will be extracted from a given structural layout. The model so obtained is suitably reduced using model order reduction techniques. As part of this effort, algorithms are developed to produce stable and passive reduced models of the original system, enabling fast frequency sweep analysis. Two distinct projection-based second order model reduction approaches will be considered: 1) matching moments, and 2) matching Laguerre coefficients, of the original system's transfer function. Further, the selection of multiple frequency shifts in these schemes to produce a globally representative model is also studied. Use of a second level preconditioned Krylov subspace process allows for a memory-efficient way to address large size problems.Ph.D.Committee Chair: Swaminathan Madhavan; Committee Member: Papapolymerou John; Committee Member: Chatterjee Abhijit; Committee Member: Peterson Andrew; Committee Member: Sitaraman Sures

Application of PEEC modeling for the development of a novel multi-gigahertz test interface with fine pitch wafer level package

Ph.DDOCTOR OF PHILOSOPH

Optimal Power Delivery Strategy in Modern VLSI Design

Department of Electrical EngineeringIn a modern very-large-scale integration (VLSI) designs, heterogeneous architectural structures and various three-dimensional (3D) integration methods have been used in a hybrid manner. Recently, the industry has combined 3D VLSI technology with the heterogeneous technology of modern VLSI called chiplet. The 3D heterogeneous architectural structure is growing attention because it reduces costs and time-to-market by increasing manufacturing yield with high integration rate and modularization. However, a main design concern of heterogeneous 3D architectural structure is power management for lowering power consumption with maintaining the required power integrity from IR drop. Although the low-power design can be realized in front-end-of-line level by reduced power supply complementary metal???oxide???semiconductor technologies, the overall low-power system performance is available with a proper design of power delivery network (PDN) for chip-level modules and system-level architectural structure. Thus, there is a demand for both the coanalysis and optimization for both chip-level and system-level. We analyzed and optimized power delivery on-chip in various 3D integration environments, and we also have proposed a chip-package-PCB coanalysis methodology at the system level. For through-silicon-via (TSV)-based 3D integration circuit (IC), We have investigated and analyzed the voltage noise in a multi-layer 3D stacking with partial element equivalent circuit (PEEC)-based on-chip PDN and frequency-dependent TSV models. We also have proposed a wire-added multi-paired on-chip PDN structure to reduce voltage noise to reduce IR drop. The performance of TSV-based 3D ICs has also been improved by reducing wake-up time through our proposed adaptive power gating strategy with tapered TSVs. For die-to-wafer 3D IC, we have proposed a power delivery pathfinding methodology, which seeks to identify a nearly optimal PDN for a given design and PDN specification. Our pathfinding methodology exploits models for routability and worst IR drop, which helps reducing iterations between PDN design and circuit design in 3D IC implementation. We also have extended the observation to system-level, we have proposed a power integrity coanalysis methodology for multiple power domains in high-frequency memory systems. Our coanalysis methodology can analyze the tendencies in power integrity by using parametric methods with consideration of package-on-package integration. We have proved that our methodology can predict similar peak-to-peak ripple voltages that are comparable with the realistic simulations of high-speed low-power memory interfaces. Finally, we have proposed analysis and optimization methodologies that are generally applicable to various integration methods used in modern VLSI designs as computer-aided-design-based solutions.clos