Analyzing and Predicting Processor Vulnerability to Soft Errors Using Statistical Techniques

The shrinking processor feature size, lower threshold voltage and increasing on-chip transistor density make current processors highly vulnerable to soft errors. Architectural Vulnerability Factor (AVF) reflects the probability that a raw soft error eventually causes a visible error in the program output, indicating the processor’s susceptibility to soft errors at architectural level. The awareness of the AVF, both at the early design stage and during program runtime, is greatly useful for designing reliable processors. However, measuring the AVF is extremely costly, resulting in large overheads in hardware, computation, and power. The situation is further exacerbated in a multi-threaded processor environment where resource contention and data sharing exist among different threads. Consequently, predicting the AVF from other easily-measured metrics becomes extraordinarily attractive to computer designers. We propose a series of AVF modeling and prediction works via using advanced statistical techniques. First, we utilize the Boosted Regression Trees (BRT) scheme to dynamically predict the AVF during program execution from a variety of performance metrics. This correlation is generalized to be across different workloads, program phases, and processor configurations on a single-threaded superscalar processor. Second, the AVF prediction is extended to multi-threaded processors where the inter-thread resource contention shows significant and non-uniform impacts on different programs; we propose a two-level predictive mechanism using BRT as building blocks to characterize the contention behavior. Finally, we employ a rule search strategy named Patient Rule Induction Method (PRIM) to explore a large processor design space at the early design stage. We are capable of generating selective rules on important configuration parameters. These rules quantify the design space subregion yielding lowest values of the response, thereby providing useful guidelines for designing reliable processors while achieving high performance

Circuit design for embedded memory in low-power integrated circuits

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2012.Cataloged from PDF version of thesis.Includes bibliographical references (p. 141-152).This thesis explores the challenges for integrating embedded static random access memory (SRAM) and non-volatile memory-based on ferroelectric capacitor technology-into lowpower integrated circuits. First considered is the impact of process variation in deep-submicron technologies on SRAM, which must exhibit higher density and performance at increased levels of integration with every new semiconductor generation. Techniques to speed up the statistical analysis of physical memory designs by a factor of 100 to 10,000 relative to the conventional Monte Carlo Method are developed. The proposed methods build upon the Importance Sampling simulation algorithm and efficiently explore the sample space of transistor parameter fluctuation. Process variation in SRAM at low-voltage is further investigated experimentally with a 512kb 8T SRAM test chip in 45nm SOI CMOS technology. For active operation, an AC coupled sense amplifier and regenerative global bitline scheme are designed to operate at the limit of on current and off current separation on a single-ended SRAM bitline. The SRAM operates from 1.2 V down to 0.57 V with access times from 400ps to 3.4ns. For standby power, a data retention voltage sensor predicts the mismatch-limited minimum supply voltage without corrupting the contents of the memory. The leakage power of SRAM forces the chip designer to seek non-volatile memory in applications such as portable electronics that retain significant quantities of data over long durations. In this scenario, the energy cost of accessing data must be minimized. This thesis presents a ferroelectric random access memory (FRAM) prototype that addresses the challenges of sensing diminishingly small charge under conditions favorable to low access energy with a time-to-digital sensing scheme. The 1 Mb IT1C FRAM fabricated in 130 nm CMOS operates from 1.5 V to 1.0 V with corresponding access energy from 19.2 pJ to 9.8 pJ per bit. Finally, the computational state of sequential elements interspersed in CMOS logic, also restricts the ability to power gate. To enable simple and fast turn-on, ferroelectric capacitors are integrated into the design of a standard cell register, whose non-volatile operation is made compatible with the digital design flow. A test-case circuit containing ferroelectric registers exhibits non-volatile operation and consumes less than 1.3 pJ per bit of state information and less than 10 clock cycles to save or restore with no minimum standby power requirement in-between active periods.by Masood Qazi.Ph.D

Sensor Buoy System for Monitoring Renewable Marine Energy Resources

[EN] In this paper we present a multi-sensor floating system designed to monitor marine energy parameters, in order to sample wind, wave, and marine current energy resources. For this purpose, a set of dedicated sensors to measure the height and period of the waves, wind, and marine current intensity and direction have been selected and installed in the system. The floating device incorporates wind and marine current turbines for renewable energy self-consumption and to carry out complementary studies on the stability of such a system. The feasibility, safety, sensor communications, and buoy stability of the floating device have been successfully checked in real operating conditions.Especially remarkable is the collaboration of the Port Authority of Valencia (Valencia port). At project completion, the prototype will become part of the weather buoy network of the Spanish state. We would also like to thank Opertek Soft SL. for analysis software assistance. This project was funded by the Spanish Ministerio de Economia, Industria y Competitividad (project reference ENE2010-21711-C02-01).García Moreno, E.; Quiles Cucarella, E.; Correcher Salvador, A.; Morant Anglada, FJ. (2018). Sensor Buoy System for Monitoring Renewable Marine Energy Resources. Sensors. 18(4):1-23. https://doi.org/10.3390/s18040945S12318

Progress Report No. 13

Progress report of the Biomedical Computer Laboratory, covering period 1 July 1976 to 30 June 1977

AN ADAPTABLE MATHEMATICAL MODEL FOR INTEGRATED NAVIGATION SYSTEMS

The project has been directed towards improving the accuracy and safety of marine navigation and ship handling, whilst contributing to reduced manning and improved fuel costs. Thus, the aim of the work was to investigate, design and develop an adaptable mathematical model that could be used in an integrated navigation system (INS) and an automatic collision avoidance system (ACAS) for use in marine vehicles. A general overview of automatic navigation is undertaken and consideration is given to the use of microprocessors on the bridge. Many of these systems now require the use of mathematical models to predict the vessels' manoeuvring characteristics: The different types and forms of models have been investigated and the derivation of their hydrodynamic coefficients is discussed in detail. The model required for an ACAS should be both accurate and adaptable, hence, extensive simulations were undertaken to evaluate the suitability of each model type. The modular model was found to have the most adaptable structure. All the modular components of this model were considered in detail to improve its adaptability, the number of non-linear terms in the hull module being reduced. A novel application, using the circulation theory to model the propeller forces and moments, allows the model to be more flexible compared to using traditional B-series four-quadrant propeller design charts. A new formula has been derived for predicting the sway and yaw components due to the propeller paddle wheel effect which gives a good degree of accuracy when comparing simulated and actual ship data, resulting in a mean positional error of less than 7%. As a consequence of this work, it is now possible for an ACAS to incorporate a ship mathematical model which produces realistic manoeuvring characteristics. Thus, the study will help to contribute to safety at sea.Kelvin Hughes Lt

Clemson Graduate School Catalog, 1988-1989

https://tigerprints.clemson.edu/grad_anncmnt/1003/thumbnail.jp

URI Undergraduate Course Catalog 1990-1991

This is a digitized, downloadable version of the University of Rhode Island Undergraduate Course Catalog.https://digitalcommons.uri.edu/course-catalogs/1038/thumbnail.jp

Aeronautical engineering: A continuing bibliography (supplement 230)

This bibliography lists 563 reports, articles and other documents introduced into the NASA scientific and technical information system in August, 1988