Miniaturized Transistors

What is the future of CMOS? Sustaining increased transistor densities along the path of Moore's Law has become increasingly challenging with limited power budgets, interconnect bandwidths, and fabrication capabilities. In the last decade alone, transistors have undergone significant design makeovers; from planar transistors of ten years ago, technological advancements have accelerated to today's FinFETs, which hardly resemble their bulky ancestors. FinFETs could potentially take us to the 5-nm node, but what comes after it? From gate-all-around devices to single electron transistors and two-dimensional semiconductors, a torrent of research is being carried out in order to design the next transistor generation, engineer the optimal materials, improve the fabrication technology, and properly model future devices. We invite insight from investigators and scientists in the field to showcase their work in this Special Issue with research papers, short communications, and review articles that focus on trends in micro- and nanotechnology from fundamental research to applications

Multigate MOSFETs for digital performance and high linearity, and their fabrication techniques

The aggressive downscaling of complementary metal–oxide–semiconductor (CMOS) technology is facing great challenges to overcome severe short-channel effects. Multigate MOSFETs are one of the most promising candidates for scaling beyond Si CMOS, due to better electrostatic control as compared to conventional planar MOSFETs. Conventional dry etching-induced surface damage is one of the main sources of performance degradation for multigate transistors, especially for III-V high mobility materials. It is also challenging to increase the fin aspect ratio by dry etching because of the non-ideal anisotropic etching profile. Here, we report a novel method, inverse metal-assisted chemical etching (i-MacEtch), in lieu of conventional RIE etching, for 3D fin channel formation. InP junctionless FinFETs with record high-aspect-ratio (~ 50:1) fins are demonstrated by this method for the first time. The i-MacEtch process flow eliminates dry-etching-induced plasma damage, high energy ion implantation damage, and high temperature annealing, allowing for the fabrication of InP fin channels with atomically smooth sidewalls. The sidewall features resulting from this unique and simplified process ensure high interface quality between high-k dielectric layer and InP fin channel. Experimental and theoretical analyses show that high-aspect-ratio FinFETs, which could deliver more current per area under much relaxed horizontal geometry requirements, are promising in pushing the technology node ahead where conventional scaling has met its physical limits. The performance of the FinFET was further investigated through numerical simulation. A new kind of FinFET with asymmetric gate and source/drain contacts has been proposed and simulated. By benchmarking with conventional symmetric FinFET, better short-channel behavior with much higher current density is confirmed. The design guidelines are provided. The overall circuit delay can be minimized by optimizing gate lengths according to different local parasites among circuits in interconnection-delay-dominated SoC applications. Continued transistor scaling requires even stronger gate electrostatic control over the channel. The ultimate scaling structure would be gate-all-around nanowire MOSFETs. We demonstrate III-V junctionless gate-all-around (GAA) nanowire (NW) MOSFETs for the first time. For the first time, source/drain (S/D) resistance and thermal budget are minimized by regrowth using metalorganic chemical vapor deposition (MOCVD) in III-V MOSFETs. The fabricated short-channel (Lg=80 nm) GaAs GAA NWFETs with extremely narrow nanowire width (WNW= 9 nm) show excellent transconductance (gm) linearity at biases (300 mV), characterized by the high third intercept point (2.6 dBm). The high linearity is especially important for low power applications because it is insensitive to bias conditions

Monolayer Doping for Fabrication of Recessed Channel MOSFETs

Scaling of semiconductor devices has become a challenge with respect to the design, device performance, reliability, integration and fabrication schemes. For over sixty-years now, from the first design of transistor various challenges has been overcome with various integration schemes to shrink the device whilst increasing the device performance. As the devices are shrinking, there is a need to achieve shallow junctions for better performance of non-planar structures such as FinFETs and 3D FETs. The implementation of conventional doping technique ion-implantation can be a hindering process for the shallow junctions as they tend to damage the crystal due to bombardment of high energy beams. Monolayer doping can be an alternative doping technique as the chemicals react with the semiconductor surface enabling a self-assembled and self-limiting process. MLD exploits the surface reaction properties of the crystalline semiconductors to form covalently bonded, self-assembled dopant molecular monolayers on the semiconductor surface with high doping concentrations. Monolayer doping is implemented to fabricate Recessed Channel MOSFETs which are successful in suppressing the short channel effects by having the channel engineered by implementing the recessed channel grooves which have the potential of reducing the corner barrier effect in comparison to a standard classical planar MOSFET. The subthreshold slope of a 10 µm planar NMOSFET previously fabricated at R.I.T was 150mV/dec, whereas for a 10 µm recessed channel MOSFET fabricated in this work was 117.65mV/dec. The threshold voltage of the 10 µm planar NMOSFET was -0.3V whereas the threshold voltage of the 10 µm recessed channel MOSFETs was 0.2V. The smallest working Recessed Channel MOSFETs fabricated had a channel length of 1 µm. Various integration schemes can be adopted to further investigate and fabricate recessed channel MOSFETs to show better device performance

Development of a fully-depleted thin-body FinFET process

The goal of this work is to develop the processes needed for the demonstration of a fully-depleted (FD) thin-body fin field effect transistor (FinFET). Recognized by the 2003 International Technology Roadmap for Semiconductors as an emerging non-classical CMOS technology, FinFETs exhibit high drive current, reduced short-channel effects, an extreme scalability to deep submicron regimes. The approach used in this study will build on previous FinFET research, along with new concepts and technologies. The critical aspects of this research are: (1) thin body creation using spacer etchmasks and oxidation/etchback schemes, (2) use of an oxynitride gate dielectric, (3) silicon crystal orientation effect evaluation, and (4) creation of fully-depleted FinFET devices of submicron gate length on Silicon-on-Insulator (SOI) substrates. The developed process yielded functional FinFETs of both thin body and wide body variety. Electrical tests were employed to describe device behaviour, including their subthreshold characteristics, standard operation, effects of gate misalignment on device performance, and impact of crystal orientation on device drive current. The process is shown to have potential for deep submicron regimes of fin width and gate length, and provides a good foundation for further research of FinFETs and similar technologies at RIT

Simulation study of scaling design, performance characterization, statistical variability and reliability of decananometer MOSFETs

This thesis describes a comprehensive, simulation based scaling study – including device design, performance characterization, and the impact of statistical variability – on deca-nanometer bulk MOSFETs. After careful calibration of fabrication processes and electrical characteristics for n- and p-MOSFETs with 35 nm physical gate length, 1 nm EOT and stress engineering, the simulated devices closely match the performance of contemporary 45 nm CMOS technologies. Scaling to 25 nm, 18 nm and 13 nm gate length n and p devices follows generalized scaling rules, augmented by physically realistic constraints and the introduction of high-k/metal-gate stacks. The scaled devices attain the performance stipulated by the ITRS. Device a.c. performance is analyzed, at device and circuit level. Extrinsic parasitics become critical to nano-CMOS device performance. The thesis describes device capacitance components, analyzes the CMOS inverter, and obtains new insights into the inverter propagation delay in nano-CMOS. The projection of a.c. performance of scaled devices is obtained. The statistical variability of electrical characteristics, due to intrinsic parameter fluctuation sources, in contemporary and scaled decananometer MOSFETs is systematically investigated for the first time. The statistical variability sources: random discrete dopants, gate line edge roughness and poly-silicon granularity are simulated, in combination, in an ensemble of microscopically different devices. An increasing trend in the standard deviation of the threshold voltage as a function of scaling is observed. The introduction of high-k/metal gates improves electrostatic integrity and slows this trend. Statistical evaluations of variability in Ion and Ioff as a function of scaling are also performed. For the first time, the impact of strain on statistical variability is studied. Gate line edge roughness results in areas of local channel shortening, accompanied by locally increased strain, both effects increasing the local current. Variations are observed in both the drive current, and in the drive current enhancement normally expected from the application of strain. In addition, the effects of shallow trench isolation (STI) on MOSFET performance and on its statistical variability are investigated for the first time. The inverse-narrow-width effect of STI enhances the current density adjacent to it. This leads to a local enhancement of the influence of junction shapes adjacent to the STI. There is also a statistical impact on the threshold voltage due to random STI induced traps at the silicon/oxide interface

Top-down engineered silicon and germanium nanowire MOSFET

Ph.DDOCTOR OF PHILOSOPH

Electrical characterization and modeling of low dimensional nanostructure FET

At the beginning of this thesis, basic and advanced device fabrication process which I haveexperienced during study such as top-down and bottom-up approach for the nanoscale devicefabrication technique have been described. Especially, lithography technology has beenfocused because it is base of the modern device fabrication. For the advanced device structure,etching technique has been investigated in detail.The characterization of FET has been introduced. For the practical consideration in theadvanced FET, several parameter extraction techniques have been introduced such as Yfunction,split C-V etc.FinFET is one of promising alternatives against conventional planar devices. Problem ofFinFET is surface roughness. During the fabrication, the etching process induces surfaceroughness on the sidewall surfaces. Surface roughness of channel decreases the effectivemobility by surface roughness scattering. With the low temperature measurement andmobility analysis, drain current through sidewall and top surface was separated. From theseparated currents, effective mobilities were extracted in each temperature conditions. Astemperature lowering, mobility behaviors from the transport on each surface have differenttemperature dependence. Especially, in n-type FinFET, the sidewall mobility has strongerdegradation in high gate electric field compare to top surface. Quantification of surfaceroughness was also compared between sidewall and top surface. Low temperaturemeasurement is nondestructive characterization method. Therefore this study can be a propersurface roughness measurement technique for the performance optimization of FinFET.As another quasi-1 D nanowire structure device, 3D stacked SiGe nanowire has beenintroduced. Important of strain engineering has been known for the effective mobility booster.The limitation of dopant diffusion by strain has been shown. Without strain, SiGe nanowireFET showed huge short channel effect. Subthreshold current was bigger than strained SiGechannel. Temperature dependent mobility behavior in short channel unstrained device wascompletely different from the other cases. Impurity scattering was dominant in short channelunstrained SiGe nanowire FET. Thus, it could be concluded that the strain engineering is notnecessary only for the mobility booster but also short channel effect immunity.Junctionless FET is very recently developed device compare to the others. Like as JFET,junctionless FET has volume conduction. Thus, it is less affected by interface states.Junctionless FET also has good short channel effect immunity because off-state ofjunctionless FET is dominated pinch-off of channel depletion. For this, junctionless FETshould have thin body thickness. Therefore, multi gate nanowire structure is proper to makejunctionless FET.Because of the surface area to volume ratio, quasi-1D nanowire structure is good for thesensor application. Nanowire structure has been investigated as a sensor. Using numericalsimulation, generation-recombination noise property was considered in nanowire sensor.Even though the surface area to volume ration is enhanced in the nanowire channel, devicehas sensing limitation by noise. The generation-recombination noise depended on the channelgeometry. As a design tool of nanowire sensor, noise simulation should be carried out toescape from the noise limitation in advance.The basic principles of device simulation have been discussed. Finite difference method andMonte Carlo simulation technique have been introduced for the comprehension of devicesimulation. Practical device simulation data have been shown for examples such as FinFET,strongly disordered 1D channel, OLED and E-paper.At the beginning of this thesis, basic and advanced device fabrication process which I haveexperienced during study such as top-down and bottom-up approach for the nanoscale devicefabrication technique have been described. Especially, lithography technology has beenfocused because it is base of the modern device fabrication. For the advanced device structure,etching technique has been investigated in detail.The characterization of FET has been introduced. For the practical consideration in theadvanced FET, several parameter extraction techniques have been introduced such as Yfunction,split C-V etc.FinFET is one of promising alternatives against conventional planar devices. Problem ofFinFET is surface roughness. During the fabrication, the etching process induces surfaceroughness on the sidewall surfaces. Surface roughness of channel decreases the effectivemobility by surface roughness scattering. With the low temperature measurement andmobility analysis, drain current through sidewall and top surface was separated. From theseparated currents, effective mobilities were extracted in each temperature conditions. Astemperature lowering, mobility behaviors from the transport on each surface have differenttemperature dependence. Especially, in n-type FinFET, the sidewall mobility has strongerdegradation in high gate electric field compare to top surface. Quantification of surfaceroughness was also compared between sidewall and top surface. Low temperaturemeasurement is nondestructive characterization method. Therefore this study can be a propersurface roughness measurement technique for the performance optimization of FinFET.As another quasi-1 D nanowire structure device, 3D stacked SiGe nanowire has beenintroduced. Important of strain engineering has been known for the effective mobility booster.The limitation of dopant diffusion by strain has been shown. Without strain, SiGe nanowireFET showed huge short channel effect. Subthreshold current was bigger than strained SiGechannel. Temperature dependent mobility behavior in short channel unstrained device wascompletely different from the other cases. Impurity scattering was dominant in short channelunstrained SiGe nanowire FET. Thus, it could be concluded that the strain engineering is notnecessary only for the mobility booster but also short channel effect immunity.Junctionless FET is very recently developed device compare to the others. Like as JFET,junctionless FET has volume conduction. Thus, it is less affected by interface states.Junctionless FET also has good short channel effect immunity because off-state ofjunctionless FET is dominated pinch-off of channel depletion. For this, junctionless FETshould have thin body thickness. Therefore, multi gate nanowire structure is proper to makejunctionless FET.Because of the surface area to volume ratio, quasi-1D nanowire structure is good for thesensor application. Nanowire structure has been investigated as a sensor. Using numericalsimulation, generation-recombination noise property was considered in nanowire sensor.Even though the surface area to volume ration is enhanced in the nanowire channel, devicehas sensing limitation by noise. The generation-recombination noise depended on the channelgeometry. As a design tool of nanowire sensor, noise simulation should be carried out toescape from the noise limitation in advance.The basic principles of device simulation have been discussed. Finite difference method andMonte Carlo simulation technique have been introduced for the comprehension of devicesimulation. Practical device simulation data have been shown for examples such as FinFET,strongly disordered 1D channel, OLED and E-paper.SAVOIE-SCD - Bib.électronique (730659901) / SudocGRENOBLE1/INP-Bib.électronique (384210012) / SudocGRENOBLE2/3-Bib.électronique (384219901) / SudocSudocFranceF

Fabricação de protótipos de FinFETs usando métodos alternativos

Orientadores: Leandro Tiago Manera, José Alexandre DinizDissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Elétrica e de ComputaçãoResumo: Este trabalho explora métodos alternativos para fabricação de protótipos de FinFETs. Diferentes métodos de definição de fin (fresagem de máscara de Al por feixe de íon focalizado e litografia por feixe focalizado de íons de gálio) são explorados, buscando flexibilidade na definição do número de fins, bem como a altura dos fins. Diferentes estruturas de porta são aplicados nos FinFETs fabricados, com dois materiais dielétricos diferentes (SiON e TiAlON) e dois métodos diferentes para a formação de TiN como eletrodo de porta. O processo de fabricação detalhado é fornecida e discutido, com especial atenção às dificuldades e desafios enfrentados. Etapas de fabricação são cuidadosamente avaliadas, apresentando detalhes e parâmetros de forma que o processo possa ser replicado. Caracterizações morfológicas e elétricas são realizadas nos FinFETs fabricadas. Com a litografia por feixe focalizado de íons de gálio, FinFETs com nove fins em paralelo são fabricados, com largura de fin até 87nm e comportamento elétrico de transistor. Parâmetros elétricos são extraídos, tais como VTH, inclinação de sublimiar, corrente de fuga, mobilidade de portadores, RSD, função trabalho do eletrodo de porta, EOT, e outros. FinFETs com largura fin abaixo de 100nm são apresentados, com inclinação de sublimiar de 120 mV/dec e moblidade de portadores de 372 cm²/V.s, resultados que mostram uma melhoria em relação a trabalhos anteriores, mas ainda deixam espaço para otimizações. Discussões são realizadas, explicando o significado dos parâmetros extraídos, e formas de melhorar os resultados. As diferentes estruturas de porta são avaliados quanto à estabilidade dos parâmetros e densidade de corrente de fuga. Um EOT de 3.6nm é alcançado para o dieléctrico SiON, com densidade de corrente de fuga entre 177uA/cm² e 0.61mA/cm². Desenvolvimentos importantes são feitos no sentido da integração de processos e inovaçoes em termos de métodos de fabricação de protótipos. Trabalhos futuros incluem melhorias na interface de silício-dielétrico e um processo de fabricação auto alinhado para alcançar uma maior transcondutância e acoplamento entre porta e canal, e reduzir a resistência sérieAbstract: This work explores alternative methods for FinFET prototype fabrication. Different fin definition methods (Al hard mask FIB milling and Ga+ FIB lithography) are explored, aiming for flexibility in defining the number of fins, as well as fin height. Alternative gate stacks are applied in the fabricated FinFETs, with two different dielectric materials (SiON and TiAlON) and two different methods for TiN gate electrode formation. The detailed fabrication process is provided and discussed, with special attention to difficulties and challenges faced. Fabrication steps are carefully evaluated, presenting details and parameters such as that the process could be replicated. Morphological and electrical characterizations are performed on the fabricated FinFETs. With the Ga+ FIB lithography method, working FinFETs with nine parallel fins are fabricated, with fin width down to 87nm. Electrical parameters are extracted, such as VTH, subthreshold slope, leakage current, low field mobility, RSD, gate electrode work function, EOT, and others. Working FinFETs with sub-100nm fin width are presented, with subthreshold slope of 120mV/dec and low field mobility of 372cm²/v.s, results that show an improvement on previous works, but still leave room for optimizations. Discussions are performed, explaining the meaning of the extracted parameters, and ways to improve the results. The different gate stacks are evaluated regarding their parameter stability and leakage current density. An EOT of 3.6nm is achieved for the SiON dielectric, with leakage current density between 177uA/cm² and 0.61mA/cm². Important developments have been made towards process integration and novel prototype fabrication methods. Future works include silicon-dielectric interface improvements and a self aligned process to achieve increased transconductance and gate-to-channel coupling, and reduce the series resistanceMestradoEletrônica, Microeletrônica e OptoeletrônicaMestra em Engenharia Elétrica161893/2015-5CNP