Application of fuzzy integrated FMEA with product lifetime consideration for new product development in flexible electronics industry

Purpose: the aim of this paper is to minimize the risks of new product development and shorten time-to-market, particularly for high-tech enterprise where the complexity of the product generates vast amount of failure mode. Design/methodology/approach: first, the concept of Critical Consideration Factor (CCF) is introduced based on product-specific technical characteristics, expected lifetime, and yield requirement to identify and prioritize the critical failure mode in the subsequent Failure Mode and Effect Analysis (FMEA), followed by process characterization on the high-risk failure mode and Critical Parameter Management (CPM) practice to realize a robust mass production system of the developed technology. The application on the development of advanced flexible substrate and surface finishes fabrication technique is presented. Findings: through the proposed methodology, the risk level of each potential failure mode can be accurately quantified to identify the critical variables. With process characterization, reliability of the product is ensured. Consequently, significant reduction in development resources and time-to-market can be achieved. Practical implications: the development strategy allows high tech enterprises to achieve a balanced ecosystem in which value created through adaption of new technology/product can be thoroughly captured through commercialization in a timely manner with no field failure. Originality/value: the proposed development strategy utilizes a unique approach with thorough considerations that enables high tech enterprise to deliver new product with rapid time-to-market without sacrificing product lifetime reliability, which is key to achieve competitive advantage in the highly dynamic market.Peer Reviewe

Fundamental Studies of Tin Whiskering in Microelectronics Finishes

Fundamental Studies of Tin Whiskering in Microelectronics Finishes Abstract Common electronics materials, such as tin, copper, steel, and brass, are ambient reactive under common use conditions, and as such are prone to corrosion. During the early 1940s, reports of failures due to electrical shorting of components caused by `whisker' (i.e., filamentary surface protrusion) growth on many surface types - including the aforementioned metals - began to emerge. Lead alloying of tin (3-10% by weight, typically in the eutectic proportion) eliminated whiskering risk for decades, until the July 2006 adoption of the Restriction of Hazardous Substances (RoHS) directive was issued by the European Union. This directive, which has since been adopted by California and parts of China, severely restricted the use of lead (<1000 ppm) in all electrical and electronics equipment being placed on the EU market, imposing the need for developing reliable new "lead-free" alternatives to SnPb. In spite of the abundance of modern-day anecdotes chronicling whisker-related failures in satellites, nuclear power stations, missiles, pacemakers, and spacecraft navigation equipment, pure tin finishes are still increasingly being employed today, and the root cause(s) of tin whiskering remains elusive. This work describes a series of structured experiments exploring the fundamental relationships between the incidence of tin whiskering (as dependent variable) and numerous independent variables. These variables included deposition method (electroplating, electroless plating, template-based electrochemical synthesis, and various physical vapor deposition techniques, including resistive evaporation, electron beam evaporation, and sputtering), the inclusion of microparticles and organic contamination, the effects of sample geometry, and nanostructuring. Key findings pertain to correlations between sample geometry and whisker propensity, and also to the stress evolution across a series of 4"-diameter silicon wafers of varying thicknesses with respect to the degree of post-metallization whiskering. Regarding sample geometry, it was found that smaller, thinner substrates displayed a more rapid onset of whiskering immediately following metallization. Changes in wafer-level stress were not found to correlate with whiskering morphology (number, density, length) after 6 weeks of aging. This result points either to the irrelevance of macrostress in the substrate/film composite, or to a difference in whiskering mechanism for rigid substrates (whose stress gradient over time is significant) when compared with thinner, flexible susbtrates (whose stress is less variable with time). Organic contamination was found to have no appreciable effect when explicitly introduced. Furthermore, electron-beam evaporated films whiskered more readily than films deposited via electroplating from baths containing organic "brighteners." Beyond such findings, novel in themselves, our work is also unique in that we emphasize the "clean" deposition of tin (with chromium adhesion layers and copper underlayers) by vacuum-based physical vapor deposition, to circumvent the question of contamination entirely. By employing silicon substrates exclusively, we have distinguished ourselves from other works (which, for example, use copper coupons fabricated from rolled shim stock) because we have better sample-to-sample consistency in terms of material properties, machinability, and orientation

Entwicklung mikroelektronischer Kontaktierungsmethoden für Hochtemperatur-Anwendungen über 250 °C

Das Hauptziel der vorliegenden Dissertation war die Entwicklung von Methoden zur Herstellung mikroelektronischer Kontakte mit Temperaturstabilitäten über 250 °C unter Verwendung von Flip-Chip-Technologie und Drahtbond-Technologie. In der Drahtbond-Technologie bieten Palladiumdrähte gegenüber standardmäßig verwendeten Golddrähten Vorteile hinsichtlich mechanischer Stabilität und 50 % geringerer Materialkosten. Die vorliegende Arbeit präsentiert eine Studie über das Schweißverhalten von Palladiumdrähten unter Verwendung von Thermosonic-Verfahren auf galvanisch abgeschiedenen Gold-Metallisierungen. Es wurden Zuverlässigkeitsuntersuchungen an Palladiumdraht-Kontakten bis zu Temperaturen von 350 °C durchgeführt. Die mechanische Stabilität wurde durch Schertests und Zugfestigkeitstests geprüft. Zur Untersuchung des Mikrogefüges wurden Drahtbond-Querschnitte mittels Rasterelektronenmikroskopie (REM) analysiert. Ergänzend zur Drahtbond-Technologie wurde eine Methode zur Herstellung hochtemperaturbeständiger Flip-Chip-Kontaktierungen entwickelt. Durch eine Verlötung mit Lötrahmen entlang der Chip-Außenkanten wurde analog zu kommerziellen Flip-Chip-Packages eine Krümmung über das gesamte Flip-Chip-Package generiert. Durch diese Deformation, welche üblicherweise durch die Verwendung von Underfills erzeugt wird, werden thermomechanische Spannungen in den Bumps reduziert. Da die präsentierte Flip-Chip-Methode im Unterschied zu kommerziellen Flip-Chip-Verfahren keine Applikation von Underfill beinhaltet, deren Temperaturbeständigkeit bei maximal 170 °C liegt, können Einsatztemperaturen von mindestens 250 °C realisiert werden. Durch sukzessives elektrochemisches Abscheiden unterschiedlicher Metall-Schichten wurden Bumps und Lötrahmen bestehend aus einem Kupfer/Nickel/Gold/Zinn-Schichtsystem hergestellt. Diese Strukturen wurden durch einen Gold/Zinn-SLID Prozess (Solid-Liquid Interdiffusion) auf Keramiksubstrate verlötet. Mit Hilfe von FEM-Simulationen (Finite Elemente Methode) wurde die Auswirkung der Lötrahmen auf thermomechanische Spannungen in Flip-Chip-Bumps berechnet. Die Krümmung der Flip-Chip-Packages, welche als Validierungsparameter für das FEM-Modell dienten, wurde mit Hilfe optischer Interferometrie bestimmt. Zur experimentellen Untersuchung der Lötverbindungen wurden Querschnittanalysen mittels Raster-Elektronen-Mikroskopie (REM) durchgeführt. Die Zuverlässigkeit der Flip-Chip-Packages wurde durch Widerstandmessungen an Daisy-Chain-Teststrukturen nach Temperaturlagerungen bei 250 °C und Temperaturwechselzyklen zwischen -50 °C bis 175 °C geprüft.The main purpose of the presented doctoral thesis was the development of micro-contacts with a temperature resistance over 250 °C by using flip-chip technology and wire bonding technology. In wire bonding technology palladium wire, in comparison to gold wire, has the advantages of higher mechanical stability and about 50 % lower material costs. This thesis presents a detailed investigation about the process performance of thermosonic palladium wire bonding on electroplated gold metallizations. The reliabilities of the fabricated wire bonds were tested at temperatures up to 350 °C. The mechanic bond stability was determined by wire pull tests and bond shear tests. The microscopic texture of the interfaces between the wire bonds and the bond pads were determined by cross sectional scanning electron microscopy (SEM). Additional to the wire bonding technology also flip-chip technology was used for the fabrication of high temperature resistant interconnects to silicon-dies. Therefore the outer edges of the silicon-dies were contacted by a seal ring, whereby a warpage of the packages was generated similar to commercial flip-chip packages. This deformation, in general generated by the application of underfills, which have a temperature stability of maximum 170 °C, reduces thermomechanical stress in flip-chip bumps. In comparison to commercial flip-chip technology the presented flip-chip method works without the usage of underfills. Thus the fabricated packages can be operated at temperatures up to 250 °C. By the successive electrochemical plating of different metal layers bumps and seal rings consisting of a copper/nickel/gold/tin metal-stack were fabricated. These structures were connected by a high temperature resistant gold/tin-SLID solder process (Solid-Liquid Interdiffusion) to ceramic substrates. The influence of the seal rings to the thermomechanical stress in flip-chip bumps was calculated by FEM-simulations (finite elements method). The warpages of the flip-chip packages were measured by optical interferometry. These data were used for experimental validation of the FEM-model. The solder interface of the flip-chip bumps was determined by sectional scanning electron microscopy (SEM). Reliability tests were performed by permanent temperature load up to 250 °C und thermal cycles between -50 °C and 175 °C. After these loads the functionality of the bump connections was tested by measuring the electric resistance of daisy chain test structures

PCB Quality Metrics that Drive Reliability (PD 18)

Risk based technology infusion is a deliberate and systematic process which defines the analysis and communication methodology by which new technology is applied and integrated into existing and new designs, identifies technology development needs based on trends analysis and facilitates the identification of shortfalls against performance objectives. This presentation at IPC Works Asia Aerospace 2019 Events provides the audience a snapshot of quality variations in printed wiring board quality, as assessed, using experiences in processing and risk analysis of PWB structural integrity coupons. The presentation will focus on printed wiring board quality metrics used, the relative type and number of non-conformances observed and trend analysis using statistical methods. Trend analysis shows the top five non-conformances observed across PWB suppliers, the root cause(s) behind these non-conformance and suggestions of mitigation plans. The trends will then be matched with the current state of the PWB supplier base and its challenges and opportunities. The presentation further discusses the risk based SMA approaches and methods being applied at GSFC for evaluating candidate printed wiring board technologies which promote the adoption of higher throughput and faster processing technology for GSFC missions

Miniaturized, low-voltage power converters with fast dynamic response

Thesis (Ph. D.)--Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2013.Cataloged from PDF version of thesis.Includes bibliographical references (pages 216-224).This thesis introduces a two-stage architecture that combines the strengths of switched capacitor (SC) techniques (small size, light-load performance) with the high efficiency and regulation capability of switch-mode power converters. The resulting designs have a superior efficient-power density trade-off over traditional designs. These power converters can provide numerous lowvoltage outputs over a wide input voltage range with a very fast dynamic response, which are ideal for powering logic devices in the mobile and high-performance computing markets. Both design and fabrication considerations for power converters using this architecture are addressed. The results are demonstrated in a 2.4 W dc-dc converter implemented in a 180 nm CMOS IC process and co-packaged with its passive components for high-performance. The converter operates from an input voltage of 2.7 V to 5.5 V with an output voltage of /= 80% efficiency.by David Giuliano.Ph.D

Electrical and Electro-Optical Biosensors

Electrical and electro-optical biosensing technologies are critical to the development of innovative POCT devices, which can be used by both professional and untrained personnel for the provision of necessary health information within a short time for medical decisions to be determined, being especially important in an era of global pandemics. This Special Issue includes a few pioneering works concerning biosensors utilizing electrochemical impedance, localized surface plasmon resonance, and the bioelectricity of sensing materials in which the amount of analyte is pertinent to the signal response. The presented results demonstrate the potential of these label-free biosensing approaches in the detection of disease-related small-molecule metabolites, proteins, and whole-cell entities

Investigation of Cu‑Cu bonding for 2.5D and 3D system integration using self‑assembled monolayer as oxidation inhibitor

Das Cu-Cu-Bonden ist eine vielversprechende lötfreie Fine-Pitch-Verbindungstechnologie für die 2,5D- und 3D-Systemintegration. Diese Bondtechnologie wurde in den letzten Jahren intensiv untersucht und wird derzeit für miniaturisierte mikroelektronische Produkte eingesetzt. Allerdings, stellt das Cu‑Cu-Bonden zum einen sehr hohe Anforderungen an die Oberflächenplanarität und -reinheit, und zum anderen sollten die Bondpartner frei von Oxiden sein. Oxidiertes Cu erfordert erhöhte Bondparameter, um die Oxidschicht zu durchbrechen und zuverlässige Cu-Cu-Verbindungen zu erzielen. Diese Bondbedingungen sind für viele sensible Bauelemente nicht geeignet. Aus diesem Grund sollten alternative Technologien mit einer einfachen Technik zum Schutz von Cu vor Oxidation gefunden werden. In dieser Arbeit werden selbstorganisierte Monolagen (SAMs) für den Cu-Oxidationsschutz und die Verbesserung der Cu-Cu-Thermokompression- (TC) und Ultraschall- (US) Flip-Chip-Bondtechnologien untersucht. Die Experimente werden an Si-Chips mit galvanisch aufgebrachten Cu-Microbumps und Cu-Schichten durchgeführt. Die Arbeit beinhaltet die umfassende Charakterisierung der SAM für den Cu-Schutz, die Bewertung der technologischen Parameter für das TC- und US-Flip-Chip-Bonden sowie die Charakterisierung der Cu-Cu-Bondqualität (Scherfestigkeitstests, Bruchflächen- und Mikrostrukturanalysen). Eine Lagerung bei tiefen Temperaturen (bei ‑18 °C und ‑40 °C) bestätigte die langanhaltende Schutzwirkung der kurzkettigen SAMs für das galvanisch abgeschiedene Cu ohne chemisch-mechanische Politur. Der Einfluss der Tieftemperaturlagerung an Luft und der thermischen SAM-Desorption in einer Inertgasatmosphäre auf die TC-Verbindungsqualität wird im Detail analysiert. Die Idee, mit Hilfe der US-Leistung SAM mechanisch zu entfernen und gleichzeitig das US-Flip-Chip-Bonden zu starten, wurde in der Literatur bisher nicht systematisch untersucht. Die Methode ermöglicht kurze Bondzeiten, niedrige Bondtemperaturen und das Bonden an Umgebungsluft. Sowohl beim TC- als auch beim US-Flip-Chip-Bonden zeigt es sich, dass die Scherfestigkeit bei den Proben mit SAM-Passivierung um ca. 30 % höher ist als bei unbeschichteten Proben. Das Vorhandensein von Si- und Ti-Bruchflächen nach den Scherfestigkeitstests ist für die Proben mit der SAM-Passivierung typisch, was auf eine höhere Festigkeit solcher Verbindungen im Vergleich zu ungeschützten Proben schließen lässt. Die Transmissionselektronenmikroskopie (TEM) zeigt keine SAM-Spuren im zentralen Bereich der Cu-Cu-Grenzfläche nach dem US-Flip-Chip-Bonden. Die Ergebnisse dieser Arbeit zeigen die Verbesserung der Bondqualität durch den Einsatz von SAM zum Schutz des Cu vor Oxidation im Vergleich zum üblicherweise angewandten Cu-Vorätzen. Das gefundene technologische Prozessfenster für das US-Flip-Chip-Bonden an Luft bietet eine hohe Bondqualität bei 90 °C und 150 °C, bei 180 MPa, bei einer Bonddauer von 1 s an. Die in dieser Arbeit gewonnenen Erkenntnisse sind ein wichtiger Beitrag zum Verständnis des SAM-Einflusses auf Chips mit galvanischen Cu-Microbumps, bzw. Cu-Schichten, und zur weiteren Anwendung der Cu-Cu-Fine-Pitch-Bondtechnologie in der Mikroelektronik.Cu-Cu bonding is one of the most promising fine-pitch interconnect technologies with solder elimination for 2.5D and 3D system integration. This bonding technology has been intensively investigated in the last years and is currently in application for miniaturized microelectronics products. However, Cu-Cu bonding has very high demands on the sur-face planarity and purity, and the bonding partners should be oxide-free. Oxidized Cu requires elevated bonding parameters in order to break through the oxide layer and achieve reliable Cu-Cu interconnects. Those bonding conditions are undesirable for many devices (e.g. due to the temperature/pressure sensitivity). Therefore, alternative technologies with a simple technique for Cu protection from oxidation are required. Self-assembled monolayers (SAMs) are proposed for the Cu protection and the improvement of the Cu-Cu thermocompression (TC) and ultrasonic (US) flip-chip bonding technologies in this thesis. The experiments were carried out on Si dies with electroplated Cu microbumps and Cu layers. The thesis comprises the comprehensive characterization of the SAM for Cu protection, evaluation of technological parameters for TC and US flip-chip bonding as well as characterization of the Cu-Cu bonding quality (shear strength tests, fracture surface and microstructure analyses). The storage at low temperatures (at ‑18 °C and ‑40 °C) confirmed the prolonged protective effect of the short-chain SAMs for the electroplated Cu without chemical-mechanical polishing. The influence of the low-temperature storage in air and the thermal SAM desorption in an inert gas atmosphere on the TC bonding quality was analyzed in detail. The approach of using US power to mechanically remove SAM and simultaneously start the US flip-chip bonding has not been systematically investigated before. The method provides the benefit of short bonding time, low bonding temperature and bonding in ambient air. Both the TC and US flip-chip bonding results featured the shear strength that is approximately 30 % higher for the samples with SAM passivation in comparison to the uncoated samples. The presence of Si and Ti fracture surfaces after the shear strength tests is typical for the samples with the SAM passivation, which suggests a higher strength of such interconnects in comparison to the uncoated samples. The transmission electron microscopy (TEM) indicated no SAM traces at the central region of the Cu-Cu bonding interface after the US flip-chip bonding. The results of this thesis show the improvement of the bonding quality caused by the application of SAM for Cu protection from oxidation in comparison to the commonly applied Cu pre-treatments. The found technological process window for the US flip-chip bonding in air offers high bonding quality at 90 °C and 150 °C, at 180 MPa, for the bonding duration of 1 s. The knowledge gained in this thesis is an important contribution to the understanding of the SAM performance on chips with electroplated Cu microbumps/layers and further application of the Cu-Cu fine-pitch bonding technology for microelectronic devices

Bau und Qualitätssicherung von Modulen und Studie von optimierten Pixelsensordesigns für die Erneuerung des CMS-Pixeldetektors = Production and Quality Assurance of Modules and Study of optimized Pixel Sensor Designs for the Upgrade of the CMS Pixel Detector

In der vorliegenden Dissertation wird die Modulproduktion am Institut für Experimentelle Kernphysik des KIT für das Phase-I-Upgrade des CMS-Pixeldetektors im Jahr 2017 vorgestellt. Dies umfasst die gesamte Produktionskette, an deren Ende die fertigen Module stehen. Ein besonderes Augenmerk wird dabei auf die Qualitätssicherung während der Produktion gelegt. Darüber hinaus werden die Ergebnisse von Teststrahluntersuchungen von optimierten Pixelsensoren für das geplante Phase-II-Upgrade des CMS-Pixeldetektors präsentiert

TLC : une architecture photovoltaïque concentrée (CPV) au potentiel d’efficacité élevé à faible coût

Abstract: Human civilization has grown dependent on ready access to low-cost energy, but the fossil fuels that currently meet the bulk of humanity’s energy needs are causing environmental destruction, including potentially catastrophic global warming. Solar energy has to potential to halt global warming, and, if low enough in cost, to also bring the whole world’s population to a first world living standard. Silicon PV has dramatically reduced costs largely through decreasing the cost and increasing the efficiency of the silicon cells, but silicon is nearing its theoretical efficiency limits, and even if the cells were free, silicon PV would still be too expensive to meet these goals. Tandem CPV cells are roughly twice as efficient as silicon, but previous CPV designs have been unable to compete with silicon on cost in spite of the efficiency advantage. A new CPV architecture, called TLC for its trough, lens and cone concentration stages, proposed using initial concentration by a low-cost trough mirror to shrink the rest of an CPV module by 40X and thus reduce overall module costs. But before this PhD research project, TLC was only a paper study. This PhD research project was started to answer the question of whether TLC could work out as well as it appeared, or whether there were hidden flaws that precluded beating silicon PV on cost, or possibly even precluded TLC from working at all. Thesis chapter 3 details the main optical design aspects, and chapter 4 covers the design of the rest of the TLC module, including leading variations where there is more than one plausible way to achieve low cost and high reliability. The work included building a unified analytical model spreadsheet that linked known aspects of the TLC design together and estimated costs for a given design variation. Thesis chapter 5 covers the economics of the proposed design, with a focus on materials costs since these dominate PV overall costs, and a section on reliability since product lifetime strongly influences life-cycle cost. The work included building 3D-CAD models to refine the TLC design, and then the prototyping of individual parts and processes, and finally building a physical prototype of a TLC mini-module and putting it in sun. This physical confirmation was necessary because even after TLC has been “built” many times, in visualization, on paper, on spreadsheets, and then in COMSOL, until TLC was physically built, hidden flaws could arise at any time. Chapter 6 of this thesis covers the simulation and validation carried out to show that it is plausible that TLC can meet its cost targets. The conclusion of this thesis summarizes the overall project. The project was a success, producing a TLC design with high potential efficiency, very low materials cost, and low estimated process costs, with the potential to beat even the US Department of Energy’s goal for PV pricing in 2030. Ray-tracing a 3D model showed that the design could achieve high concentration with adequate acceptance angles, and tests showed that the prototyping cells were suitable for TLC’s massively parallel microcell-array receiver configuration. The project also successfully tested the proposed manufacturing process for molding semi-dense arrays of tertiary optical elements on the back of a lens tile and assembled a TLC mini module which was tested on sun at the focus of a trough mirror. Four papers have already been published, with a fifth paper accepted, as result of this work.La civilisation humaine est devenue de plus en plus dépendante d'un accès facile à une énergie à faible coût, mais les combustibles fossiles qui répondent actuellement à la majeure partie des besoins énergétiques de l'humanité causent la destruction de l'environnement, y compris un réchauffement climatique potentiellement catastrophique. L'énergie solaire a le potentiel d'arrêter le réchauffement climatique et, si son coût est suffisamment bas, d'amener également la population mondiale entière à un niveau de vie du premier monde. Les coûts de photovoltaïque (PV) à base de silicium ont été considérablement réduits en grande partie en diminuant le prix et en augmentant l'efficacité des cellules en silicium, cependant l’utilisation de silicium a ses limites d'efficacité théoriques, et même si les cellules étaient gratuites, la PV à base de silicium serait encore trop chère pour atteindre ces objectifs. Les cellules de photovoltaïque concentré (CPV) Tandem sont environ deux fois plus efficaces que celles à base de silicium, mais malgré l'avantage de leur efficacité, les architectures des années précédentes de CPV n'ont pas été en mesure de rivaliser avec le silicium en termes de coût. Une nouvelle architecture CPV, appelée TLC (Trough-Lens-Cone) utilise la concentration initiale par un miroir parabolique à faible coût combiné avec un module CPV de 40X et ainsi réduire les coûts globaux du module. Avant ce projet de recherche de doctorat, TLC n'était qu'une étude sur papier. Cette thèse a pour but de répondre à la question de savoir si l’approche TLC pouvait fonctionner aussi bien qu'elle était apparue, ou s'il y avait des défauts cachés qui empêchaient de battre le silicium PV sur le coût, ou pourrait même empêcher la TLC de fonctionner. Ce travail comprenait la construction d'un modèle de tableur unifié qui reliait les aspects connus de la conception TLC et les coûts estimés pour une variation de conception donnée. Nous présentons également la construction de modèles 3D-CAD pour raffiner la conception TLC, puis le prototypage de pièces individuelles et de processus, et enfin la construction d'un prototype physique d'un mini-module TLC qui est mis au soleil. Cette validation physique était nécessaire car même après que TLC ait été théoriquement et numériquement « construit » à plusieurs reprises soit, en visualisation, sur papier, sur des feuilles de calcul, puis dans COMSOL, avant que TLC soit physiquement construit, des défauts cachés pouvaient survenir à tout moment. La mise en œuvre de ce projet a réussi, produisant une conception TLC cohérente qui avait un rendement élevé avec un coût des matériaux très bas et des faibles coûts estimatifs de processus, avec un potentiel de battre même l’objectif du département américain de l'énergie pour la tarification du silicium photovoltaïque en 2030. Le suivi de raies (Ray-tracing) avec un modèle 3D a montré que la conception pouvait atteindre une concentration élevée avec des angles d'acceptation adéquats. Les tests ont également montré que les cellules de prototypage ont été bien adaptées à la nouvelle configuration de TLC de récepteur à matrice de microcellules massivement parallèle. Le projet a également testé avec succès le processus de fabrication proposé pour le moulage de réseaux semi-denses d'éléments optiques tertiaires à l'arrière d'un carreau de lentille. Le projet a également réussi à assembler un mini-module TLC et à tester sous le soleil avec le focus d'un miroir parabolique. Quatre articles ont déjà été publiés, avec un cinquième article accepté, à la suite de ce travail