Reliability Studies of TiN/Hf-Silicate Based Gate Stacks

Hafnium-silicate based oxides are among the leading candidates to be included into the first generation of high-Κ gate stacks in nano-scale CMOS technology because of their distinct advantages as far as thermal stability, leakage characteristics, threshold stability and low mobility degradation are concerned. Their reliability, which is limited by trapping at pre-existing and stress induced defects, remains to be a major concern. Energy levels of electrically active ionic defects within the thick high-Κ have been experimentally observed in the context of MOS band diagram for the first time in Hf-silicate gate stacks from low temperature and leakage measurements. Excellent match between experimental and calculated defect levels shows that bulk O vacancies are probably responsible for electron trapping at both shallow and deep levels. Their role in trapping and transport under different gate polarity and band bending conditions has been determined. For gate injection, electron transport through mid-gap states dominates, which leads to slow transient trapping at deep levels. Under substrate injection field and temperature dependent transport through conduction-edge shallow levels or trap-assisted tunneling due to negative- U transition occurs depending on bias condition. The former gives rise to fast transient trapping, whereas the latter is responsible for slow transient trapping. Mixed degradation, due to trapping of both electrons and holes in the trap levels within the bulk high-K, was observed under constant voltage stress (CVS) applied on n-channel MOS capacitors with negative bias condition. Mixed degradation resulted in turn-around effect in flat-band voltage shift (ΔFB) with respect to stress time. Under CVS with positive bias, applied on nMOSFETs, lateral distribution of trapped charges in the deep levels causes turn-around effect in threshold voltage shift (ΔVT) with respect to stress levels. For the incident carrier energies above the calculated 0 vacancy formation threshold and thick high-Κ layer, both flatband voltage shift, due to electron trapping at the deep levels, and increase in leakage current during stress follow tn(n ≈ 0.4) power-law dependence under substrate hot electron injection. Negative-U transitions to deep levels are shown to be responsible for the strong correlation between slow transient trapping and trap assisted tunneling. As far as negative bias temperature instability, NBTI effects on pMOSFETs is concerned, ΔVT is due to the mixed degradation within the bulk high-Κ for low bias conditions. For moderately high bias, ΔVT shows an excellent match with that of SiO, based devices, which is explained by reaction-diffusion (R-D) model of NBTL. Under high bias condition at elevated temperatures, due to high Si-H bond-annealing/bond-breaking ratio, the experimentally observed absence of the impact ionization induced hot holes at the interfacial layer (IL)/Si interface probably limits the interface state generation and ΔVT as they quickly reach saturation. Time-zero dielectric breakdown (TZBD) characteristics of TiN/HfO2 based gate stacks show that thickness and growth conditions significantly affect the BD field of IL. For the thin high-w layers, BD of IL triggers BD of the gate stack. Otherwise, BD of high-w layer initiates it. During time dependent dielectric breakdown, TDDB, four regimes of degradation are observed under CVS with high gate bias conditions: (i) charge trapping/defect generation, (ii) soft breakdown (SBD), (iii) progressive breakdown and (iv) hard breakdown (HBD). Activation energy of bond-breakage, found from Arrhenius plots of 63% failure value of TBD, shows that IL degradation triggers gate stacks BD, and the wear-out during TDDB

Gate oxide failure in MOS devices

The thesis presents an experimental and theoretical investigation of gate oxide breakdown in MOS networks, with a particular emphasis on constant voltage overstress failure. It begins with a literature search on gate oxide failure mechanisms, particularly time-dependent dielectric breakdown, in MOS devices. The experimental procedure is then reported for the study of gate oxide breakdown under constant voltage stress. The experiments were carried out on MOSFETs and MOS capacitor structures, recording the characteristics of the devices before and after the stress. The effects of gate oxide breakdown in one of the transistors in an nMOS inverter were investigated and several parameters were found to have changed. A mathematical model for oxide breakdown, based on physical mechanisms, is proposed. Both electron and hole trapping occurred during the constant voltage stress. Breakdown appears to take place when the trapped hole density reach a critical value. PSPICE simulations were performed for the MOSFETs, nMOS inverter and CMOS logic circuits. Two models of MOSFET with gate oxide short were validated. A good agreement between experiments and simulations was achieved

Cmos Rf Cituits Sic] Variability And Reliability Resilient Design, Modeling, And Simulation

The work presents a novel voltage biasing design that helps the CMOS RF circuits resilient to variability and reliability. The biasing scheme provides resilience through the threshold voltage (VT) adjustment, and at the mean time it does not degrade the PA performance. Analytical equations are established for sensitivity of the resilient biasing under various scenarios. Power Amplifier (PA) and Low Noise Amplifier (LNA) are investigated case by case through modeling and experiment. PTM 65nm technology is adopted in modeling the transistors within these RF blocks. A traditional class-AB PA with resilient design is compared the same PA without such design in PTM 65nm technology. Analytical equations are established for sensitivity of the resilient biasing under various scenarios. A traditional class-AB PA with resilient design is compared the same PA without such design in PTM 65nm technology. The results show that the biasing design helps improve the robustness of the PA in terms of linear gain, P1dB, Psat, and power added efficiency (PAE). Except for post-fabrication calibration capability, the design reduces the majority performance sensitivity of PA by 50% when subjected to threshold voltage (VT) shift and 25% to electron mobility (μn) degradation. The impact of degradation mismatches is also investigated. It is observed that the accelerated aging of MOS transistor in the biasing circuit will further reduce the sensitivity of PA. In the study of LNA, a 24 GHz narrow band cascade LNA with adaptive biasing scheme under various aging rate is compared to LNA without such biasing scheme. The modeling and simulation results show that the adaptive substrate biasing reduces the sensitivity of noise figure and minimum noise figure subject to process variation and iii device aging such as threshold voltage shift and electron mobility degradation. Simulation of different aging rate also shows that the sensitivity of LNA is further reduced with the accelerated aging of the biasing circuit. Thus, for majority RF transceiver circuits, the adaptive body biasing scheme provides overall performance resilience to the device reliability induced degradation. Also the tuning ability designed in RF PA and LNA provides the circuit post-process calibration capability

Process development and reliability of thin gate oxides

The Semiconductor Industry Association\u27s (SIA) current National Technological Roadmap calls for the development of a suitable dielectric material for use in gate oxide for the 0.18|micrometers generation of chips and beyond. Some of the key challenges identified are resistance to oxide trapped charge generation from higher levels of tunneling currents and/or plasma processing, and formation of an effective barrier to dopant penetration during the gate processing. One promising material to meet these challenges is nitrided thermal oxide. Development of a growth process that yields high quality, lOnm thick, thermally grown Si02 films at RJT for use as a gate dielectric is described. Thin oxides (8nm - 20nm) were grown by thermal oxidation followed by inert anneals in Ar and N2. Nitrided oxides were created by implanting N2 (dose range: 5el3 - lei 5 /cm2) into the substrate prior to gate oxidation. Test equipment was setup to study Fowler Nordheim (FN) tunneling and dielectric breakdown. Test structures consisted of conventional and novel MOS capacitor structures with aluminum and poly-silicon gate electrodes. Scaling RJT\u27s existing, 20nm oxidation process to lOnm resulted in degradation of dielectric strength from \u3e lOMV/cm to ~6-7MV/cm for Al-gate MOS capacitors. Replacing the Al gate material with poly-silicon restored the dielectric strength to lOMV/cm. Performing an N2 implant through a screening oxide, prior to gate oxidation, was investigated as a means of obtaining a nitrided thermal oxide. For certain doses (5el3 - 5el4 /cm2), Al-gate MOS capacitors exhibited an improved dielectric strength as the mean value increased from 6- 7MV/cm to ~9MV/cm. Poly-Si gate MOS capacitors showed a similar improvement for the nitrided oxides, exhibiting mean dielectric strength values in the 10-12MV/cm range. Fowler- Nordheim (FN) tunnel current measurements showed that the nitrided films exhibit lower leakage levels and less charge trapping than their thermal Si02 counterparts. Results indicate that a 12nm nitrided oxide, for a certain dose (5el4/cm2), exhibited equivalent electrical performance to a 20nm thermally grown Si02 oxide. In conclusion, a process was developed for yielding reliable thin gate oxides (~10nm) in a university fab

Defect Induced Aging and Breakdown in High-k Dielectrics

abstract: High-k dielectrics have been employed in the metal-oxide semiconductor field effect transistors (MOSFETs) since 45 nm technology node. In this MOSFET industry, Moore’s law projects the feature size of MOSFET scales half within every 18 months. Such scaling down theory has not only led to the physical limit of manufacturing but also raised the reliability issues in MOSFETs. After the incorporation of HfO2 based high-k dielectrics, the stacked oxides based gate insulator is facing rather challenging reliability issues due to the vulnerable HfO2 layer, ultra-thin interfacial SiO2 layer, and even messy interface between SiO2 and HfO2. Bias temperature instabilities (BTI), hot channel electrons injections (HCI), stress-induced leakage current (SILC), and time dependent dielectric breakdown (TDDB) are the four most prominent reliability challenges impacting the lifetime of the chips under use. In order to fully understand the origins that could potentially challenge the reliability of the MOSFETs the defects induced aging and breakdown of the high-k dielectrics have been profoundly investigated here. BTI aging has been investigated to be related to charging effects from the bulk oxide traps and generations of Si-H bonds related interface traps. CVS and RVS induced dielectric breakdown studies have been performed and investigated. The breakdown process is regarded to be related to oxygen vacancies generations triggered by hot hole injections from anode. Post breakdown conduction study in the RRAM devices have shown irreversible characteristics of the dielectrics, although the resistance could be switched into high resistance state.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

DEEP SUBMICRON CMOS VLSI CIRCUIT RELIABILITY MODELING, SIMULATION AND DESIGN

CMOS VLSI circuit reliability modeling and simulation have attracted intense research interest in the last two decades, and as a result almost all IC Design For Reliability (DFR) tools now try to incrementally simulate device wearout mechanisms in iterative ways. These DFR tools are capable of accurately characterizing the device wearout process and predicting its impact on circuit performance. Nevertheless, excessive simulation time and tedious parameter testing process often limit popularity of these tools in product design and fabrication. This work develops a new SPICE reliability simulation method that shifts the focus of reliability analysis from device wearout to circuit functionality. A set of accelerated lifetime models and failure equivalent circuit models are proposed for the most common MOSFET intrinsic wearout mechanisms, including Hot Carrier Injection (HCI), Time Dependent Dielectric Breakdown (TDDB), and Negative Bias Temperature Instability (NBTI). The accelerated lifetime models help to identify the most degraded transistors in a circuit in terms of the device's terminal voltage and current waveforms. Then corresponding failure equivalent circuit models are incorporated into the circuit to substitute these identified transistors. Finally, SPICE simulation is performed again to check circuit functionality and analyze the impact of device wearout on circuit operation. Device wearout effects are lumped into a very limited number of failure equivalent circuit model parameters, and circuit performance degradation and functionality are determined by the magnitude of these parameters. In this new method, it is unnecessary to perform a large number of small-step SPICE simulation iterations. Therefore, simulation time is obviously shortened in comparison to other tools. In addition, a reduced set of failure equivalent circuit model parameters, rather than a large number of device SPICE model parameters, need to be accurately characterized at each interim wearout process. Thus device testing and parameter extraction work are also significantly simplified. These advantages will allow circuit designers to perform quick and efficient circuit reliability analyses and to develop practical guidelines for reliable electronic designs

Electrical characterization of high-k gate dielectrics for advanced CMOS gate stacks

The oxide/substrate interface quality and the dielectric quality of metal oxide semiconductor (MOS) gate stack structures are critical to future CMOS technology. As SiO2 was replaced by the high-k dielectric to further equivalent oxide thickness (EOT), high mobility substrates like Ge have attracted increasing in replacing Si substrate to further enhance devices performance. Precise control of the interface between high-k and the semiconductor substrate is the key of the high performance of future transistor. In this study, traditional electrical characterization methods are used on these novel MOS devices, prepared by advanced atomic layer deposition (ALD) process and with pre and post treatment by plasma generated by slot plane antenna (SPA). MOS capacitors with a TiN metal gate/3 nm HfAlO/0.5 nm SiO2/Si stacks were fabricated by different Al concentration, and different post deposition treatments. A simple approach is incorporated to correct the error, introduced by the series resistance (Rs) associated with the substrate and metal contact. The interface state density (Dit), calculated by conductance method, suggests that Dit is dependent on the crystalline structure of hafnium aluminum oxide film. The amorphous structure has the lowest Dit whereas crystallized HfO2 has the highest Dit. Subsequently, the dry and wet processed interface layers for three different p type Ge/ALD 1nm-Al2O3/ALD 3.5nm-ZrO2/ALD TiN gate stacks are studied at low temperatures by capacitance-voltage (CV),conductance-voltage (GV) measurement and deep level transient spectroscopy (DLTS). Prior to high-k deposition, the interface is treated by three different approaches (i) simple chemical oxidation (Chemox); (ii) chemical oxide removal (COR) followed by 1 nm oxide by slot-plane-antenna (SPA) plasma (COR&SPAOx); and (iii) COR followed by vapor O3 treatment (COR&O3). Room temperature measurement indicates that superior results are observed for slot-plane-plasma-oxidation processed samples. The reliability of TiN/ZrO2/Al2O3/p-Ge gate stacks is studied by time dependent dielectric breakdown (TDDB). High-k dielectric is subjected to the different slot plane antenna oxidation (SPAO) processes, namely, (i) before high-k ALD (Atomic Layer Deposition), (ii) between high-k ALD, and (iii) after high-k ALD. High-k layer and interface states are improved due to the formation of GeO2 by SPAO when SPAO is processed after high-k. GeO2 at the interface can be degraded easily by substrate electron injection. When SPAO is processed between high-k layers, a better immunity of interface to degradation was observed under stress. To further evaluate the high-k dielectrics and how EOT impacts on noise mechanism time zero 1/f noise is characterized on thick and thin oxide FinFET transistors, respectively. The extracted noise models suggest that as a function of temperatures and bias conditions the flicker noise mechanism tends to be carrier number fluctuation model (McWhorter model). Furthermore, the noise mechanism tends to be mobility fluctuation model (Hooge model) when EOT reduces

Secure HfO2 based charge trap EEPROM with lifetime and data retention time modeling

Trusted computing is currently the most promising security strategy for cyber physical systems. Trusted computing platform relies on securely stored encryption keys in the on-board memory. However, research and actual cases have shown the vulnerability of the on-board memory to physical cryptographic attacks. This work proposed an embedded secure EEPROM architecture employing charge trap transistor to improve the security of storage means in the trusted computing platform. The charge trap transistor is CMOS compatible with high dielectric constant material as gate oxide which can trap carriers. The process compatibility allows the secure information containing memory to be embedded with the CPU. This eliminates the eavesdropping and optical observation. This effort presents the secure EEPROM cell, its high voltage programming control structure and an interface architecture for command and data communication between the EEPROM and CPU. The interface architecture is an ASIC based design that exclusively for the secure EEPROM. The on-board programming capability enables adjustment of programming voltages and accommodates EEPROM threshold variation due to PVT to optimize lifetime. In addition to the functional circuitry, this work presents the first model of lifetime and data retention time tradeoff for this new type of EEPROM. This model builds the bridge between desired data retention time and lifetime while producing the corresponding programming time and voltage