Increasing the robustness of digital circuits with ring oscillator clocks

Technology scaling enables lower supply voltages, but also increases power density of integrated circuits. In this context, power integrity becomes a major concern in the implementation of highperformance designs. This paper analyzes the influence of Ring Oscillator Clocks (ROCs) on mitigating the impacts of voltage noise. A design with an ROC as the clock source is able to work correctly even in the presence of severe and unpredictable voltage emergencies, without degrading the average performance and power metrics of the circuit. ROCs offer an instantaneous and continuous adaptation to the environment conditions, thus reducing the margins used to prevent timing failures. ROCs provide robustness independently of the power delivery network, thus relaxing the constraints required for the design of the PCB and package. As a by-product, the inherent jitter generated by ROCs produces a spreadspectrum effect that reduces electromagnetic emissions.Peer ReviewedPostprint (published version

Towards High Efficiency and High Power Density Converter: System Level Design, Modulation, and Active EMI Filters

Power converter exposes strong challenges to its efficiency, power density and reliability. For the grid-connected inverter application, three-level (3-L) T-type neutral-point-clamped (TNPC) inverters has higher efficiency and lower total harmonic distortion (THD) compared to two-level inverter. Hybrid switch concept combines the benefit of both silicon carbide (SiC) MOSFET and Si IGBT. By applying hybrid switch structure in 3-L T-type inverter, the total power density of 3-L TNPC inverter will be higher while the cost will be lower than that of all-SiC 3-L T-type inverter. The hybrid switch based 3-L TNPC inverter also imposes challenge to its modulation and control, a propoer modulation and control shceme need to be chosen to enable better inverter performance in terms of efficiency, neutral point balancing and electromagnetic interference (EMI). Morever, to shrink the EMI filter size for the power converter, an active EMI filter (AEF) structure is proposed. The proposed AEF provides superior performance than any of the conventional passive EMI filter and the existing AEFs. In this work, the system level design and testing of a 30 kW grid-connected 3-L T-type inverter with hybrid switch structure is discussed. Then, an improved space vector modulation (SVM) has been proposed, which enables neutral-point balancing (NPB) control in the proposed hybrid-switch-based TNPC inverters with loss and common-mode voltage reduction. Finally, the design, modelling, and testing of the proposed AEF is demonstrated

Electromagnetic Interference and Compatibility

Recent progress in the fields of Electrical and Electronic Engineering has created new application scenarios and new Electromagnetic Compatibility (EMC) challenges, along with novel tools and methodologies to address them. This volume, which collects the contributions published in the “Electromagnetic Interference and Compatibility” Special Issue of MDPI Electronics, provides a vivid picture of current research trends and new developments in the rapidly evolving, broad area of EMC, including contributions on EMC issues in digital communications, power electronics, and analog integrated circuits and sensors, along with signal and power integrity and electromagnetic interference (EMI) suppression properties of materials

Power Reductions with Energy Recovery Using Resonant Topologies

The problem of power densities in system-on-chips (SoCs) and processors has become more exacerbated recently, resulting in high cooling costs and reliability issues. One of the largest components of power consumption is the low skew clock distribution network (CDN), driving large load capacitance. This can consume as much as 70% of the total dynamic power that is lost as heat, needing elaborate sensing and cooling mechanisms. To mitigate this, resonant clocking has been utilized in several applications over the past decade. An improved energy recovering reconfigurable generalized series resonance (GSR) solution with all the critical support circuitry is developed in this work. This LC resonant clock driver is shown to save about 50% driver power (\u3e40% overall), on a 22nm process node and has 50% less skew than a non-resonant driver at 2GHz. It can operate down to 0.2GHz to support other energy savings techniques like dynamic voltage and frequency scaling (DVFS). As an example, GSR can be configured for the simpler pulse series resonance (PSR) operation to enable further power saving for double data rate (DDR) applications, by using de-skewing latches instead of flip-flop banks. A PSR based subsystem for 40% savings in clocking power with 40% driver active area reduction xii is demonstrated. This new resonant driver generates tracking pulses at each transition of clock for dual edge operation across DVFS. PSR clocking is designed to drive explicit-pulsed latches with negative setup time. Simulations using 45nm IBM/PTM device and interconnect technology models, clocking 1024 flip-flops show the reductions, compared to non-resonant clocking. DVFS range from 2GHz/1.3V to 200MHz/0.5V is obtained. The PSR frequency is set \u3e3× the clock rate, needing only 1/10th the inductance of prior-art LC resonance schemes. The skew reductions are achieved without needing to increase the interconnect widths owing to negative set-up times. Applications in data circuits are shown as well with a 90nm example. Parallel resonant and split-driver non-resonant configurations as well are derived from GSR. Tradeoffs in timing performance versus power, based on theoretical analysis, are compared for the first time and verified. This enables synthesis of an optimal topology for a given application from the GSR

Analysis of Electromagnetic Interference Problems Caused by Split Reference Plane on High-Speed Multilayer Boards

Digital/Analog Ground Partitioning Has Been Used to Isolate Noisy Digital and Power Current from Sensitive Analog Currents in High-Speed Multiplayer Printed Circuit Boards. This Design, However, Breaks the Current Return Path for Signal Traces that Cross the Two Separated Grounds, Which Causes Undesired Effects Such as Signal Distortion and Radiated Emission. Electromagnetic Mechanism Associated with Them Needs to Be Understood to Control and Suppress These Undesired Effects. in This Paper, Equivalent Circuit Diagrams Are Presented to Explain the Current Path in a Practical Camera Device with the Separated Ground. Finally, Optimal Stitching Via Locations is Determined to Provide a Good Return Current Path and Thus Suppress the Radiated Emission. Numerical Simulations Are Conducted for Validation in Frequency Ranges from 10MHz to 2GHz

A GaN-Based Synchronous Rectifier with Reduced Voltage Distortion for 6.78 MHz Wireless Power Applications

The call for a larger degree of engineering innovation grows as wireless power transfer increases in popularity. In this thesis, 6.78 MHz resonant wireless power transfer is explained. Challenges in WPT such as dynamic load variation and electromagnetic interference due to harmonic distortion are discussed, and a literature review is conducted to convey how the current state of the art is addressing these challenges.A GaN-based synchronous rectifier is proposed as a viable solution, and a model of the circuit is constructed. The precisely derived model is compared to a linearized model to illustrate the importance of exactness within the model derivation. The model is then used to quantify the design space of circuit parameters Lr and Cr with regard to harmonic distortion, input phase control, and efficiency. Practical design decisions concerning the 6.78 MHz system are explained. These include gate driver choice and mitigation of PCB parasitics. The model is verified with open loop experimentation using a linear power amplifier, FPGA, electronic load, and two function generators. Current zero-crossing sensing is then introduced in order to achieve self-regulation of both the switching frequency and input phase. The details of the FPGA code and sensing scheme used to obtain this closed loop functionality are described in detail. Finally, conclusions are drawn, and future work is identified

Aircraft electromagnetic compatibility

Illustrated are aircraft architecture, electromagnetic interference environments, electromagnetic compatibility protection techniques, program specifications, tasks, and verification and validation procedures. The environment of 400 Hz power, electrical transients, and radio frequency fields are portrayed and related to thresholds of avionics electronics. Five layers of protection for avionics are defined. Recognition is given to some present day electromagnetic compatibility weaknesses and issues which serve to reemphasize the importance of EMC verification of equipment and parts, and their ultimate EMC validation on the aircraft. Proven standards of grounding, bonding, shielding, wiring, and packaging are laid out to help provide a foundation for a comprehensive approach to successful future aircraft design and an understanding of cost effective EMC in an aircraft setting

The ac power system testbed

The object of this program was to design, build, test, and deliver a high frequency (20 kHz) Power System Testbed which would electrically approximate a single, separable power channel of an IOC Space Station. That program is described, including the technical background, and the results are discussed showing that the major assumptions about the characteristics of this class of hardware (size, mass, efficiency, control, etc.) were substantially correct. This testbed equipment was completed and delivered and is being operated as part of the Space Station Power System Test Facility