Linearized 9-Bit Hybrid LBDD PWM Modulator for Digital Class-BD Amplifier

The paper presents an original architecture andimplementation of 9-bit Linearized Pulse Width Modulator(LPWM) for Class-BD amplifier, based on the hybrid methodusing STM32 microcontroller and Programmable Tapped DelayLine (PTDL). The analog input signals are converted into 12-bitPCM signals, then are directly transformed into 32-bit LBDDDPWM data of the pulse-edge locations within n-th period of theswitching frequency, next requantized to the 9-bit digitaloutputs, and finally converted into the two physical trains of 1-bitPWM signals, to control the output stage of the Class-BD audioamplifier. The hybrid 9-bit quantizer converts 6 MSB bits usingcounter method, based on the peripherals of STM32microcontroller, while the remaining 3 LSB bits - using a methodbased on the PTDL. In the paper extensive verification ofalgorithm and circuit operation as well as simulation inMATLAB and experimental results of the proposed 9-bit hybridLBDD DPWM circuit have been performed. It allows to attainSNR of 80 dB and THD about 0,3% within the audio baseband

A detailed analysis of the imperfections of pulsewidth modulated waveforms on the output stage of a class D audio amplifier

Thesis (PhD (Electrical and Electronic Engineering))--University of Stellenbosch, 2009.Although the Class D topology offers several advantages, its use in audio amplification has previously been limited by the lack of competitiveness in fidelity compared to its linear counterparts. During the past decade, technological advances in semiconductor technology have awakened new interest since competitive levels of distortion could now be achieved. The output stage of such an amplifier is the primary limiting factor in its performance. In this dissertation, four non-ideal effects existing in this stage are identified and mathematically analysed. The analytical analysis makes use of a well-established mathematical model, based on the double Fourier series method, to model the imperfections introduced into a naturally sampled pulsewidth modulated waveform. The analysis is complemented by simulation using a strategy based on Newton’s numerical method. The theory is verified by a comparison between the analytical-, simulated- and experimental results

Design and Implementation of Switching Voltage Integrated Circuits Based on Sliding Mode Control

The need for high performance circuits in systems with low-voltage and low-power requirements has exponentially increased during the few last years due to the sophistication and miniaturization of electronic components. Most of these circuits are required to have a very good efficiency behavior in order to extend the battery life of the device. This dissertation addresses two important topics concerning very high efficiency circuits with very high performance specifications. The first topic is the design and implementation of class D audio power amplifiers, keeping their inherent high efficiency characteristic while improving their linearity performance, reducing their quiescent power consumption, and minimizing the silicon area. The second topic is the design and implementation of switching voltage regulators and their controllers, to provide a low-cost, compact, high efficient and reliable power conversion for integrated circuits. The first part of this dissertation includes a short, although deep, analysis on class D amplifiers, their history, principles of operation, architectures, performance metrics, practical design considerations, and their present and future market distribution. Moreover, the harmonic distortion of open-loop class D amplifiers based on pulse-width modulation (PWM) is analyzed by applying the duty cycle variation technique for the most popular carrier waveforms giving an easy and practical analytic method to evaluate the class D amplifier distortion and determine its specifications for a given linearity requirement. Additionally, three class D amplifiers, with an architecture based on sliding mode control, are proposed, designed, fabricated and tested. The amplifiers make use of a hysteretic controller to avoid the need of complex overhead circuitry typically needed in other architectures to compensate non-idealities of practical implementations. The design of the amplifiers based on this technique is compact, small, reliable, and provides a performance comparable to the state-of-the-art class D amplifiers, but consumes only one tenth of quiescent power. This characteristic gives to the proposed amplifiers an advantage for applications with minimal power consumption and very high performance requirements. The second part of this dissertation presents the design, implementation, and testing of switching voltage regulators. It starts with a description and brief analysis on the power converters architectures. It outlines the advantages and drawbacks of the main topologies, discusses practical design considerations, and compares their current and future market distribution. Then, two different buck converters are proposed to overcome the most critical issue in switching voltage regulators: to provide a stable voltage supply for electronic devices, with good regulation voltage, high efficiency performance, and, most important, a minimum number of components. The first buck converter, which has been designed, fabricated and tested, is an integrated dual-output voltage regulator based on sliding mode control that provides a power efficiency comparable to the conventional solutions, but potentially saves silicon area and input filter components. The design is based on the idea of stacking traditional buck converters to provide multiple output voltages with the minimum number of switches. Finally, a fully integrated buck converter based on sliding mode control is proposed. The architecture integrates the external passive components to deliver a complete monolithic solution with minimal silicon area. The buck converter employs a poly-phase structure to minimize the output current ripple and a hysteretic controller to avoid the generation of an additional high frequency carrier waveform needed in conventional solutions. The simulated results are comparable to the state-of-the-art works even with no additional post-fabrication process to improve the converter performance

Mathematical models for class-D amplifiers

We here analyse a number of class-D amplifier topologies. Class-D amplifiers operate by converting an audio input signal into a high-frequency square wave output, whose lower-frequency components can accurately reproduce the input. Their high power efficiency and potential for low distortion makes them suitable for use in a wide variety of electronic devices. By calculating the outputs from a classical class-D design implementing different sampling schemes we demonstrate that a more recent method, called the Fourier transform/Poisson resummation method, has many advantages over the double Fourier series method, which is the traditional technique employed for this analysis. We thereby show that when natural sampling is used the input signal is reproduced exactly in the low-frequency part of the output, with no distortion. Although this is a known result, our calculations present the method and notation that we later develop. The classical class-D design is prone to noise, and therefore negative feedback is often included in the circuit. Subsequently we incorporate the Fourier transform/Poisson resummation method into a formalised and succinct analysis of a first-order negative feedback amplifier. Using perturbation expansions we derive the audio-frequency part of the output, demonstrating that negative feedback introduces undesirable distortion. Here we reveal the next order terms in the output compared with previous work, giving further insight into the nonlinear distortion. We then further extend the analysis to examine two more complex negative feedback topologies, namely a second-order and a derivative negative feedback design. Modelling each of these amplifiers presents an increased challenge due to the differences in their respective circuit designs, and in addition, for the derivative negative feedback amplifier we must consider scaling regimes based on the relative magnitudes of the frequencies involved. For both designs we establish novel expressions for the output, including the most significant distortion terms

Mathematical models for class-D amplifiers

We here analyse a number of class-D amplifier topologies. Class-D amplifiers operate by converting an audio input signal into a high-frequency square wave output, whose lower-frequency components can accurately reproduce the input. Their high power efficiency and potential for low distortion makes them suitable for use in a wide variety of electronic devices. By calculating the outputs from a classical class-D design implementing different sampling schemes we demonstrate that a more recent method, called the Fourier transform/Poisson resummation method, has many advantages over the double Fourier series method, which is the traditional technique employed for this analysis. We thereby show that when natural sampling is used the input signal is reproduced exactly in the low-frequency part of the output, with no distortion. Although this is a known result, our calculations present the method and notation that we later develop. The classical class-D design is prone to noise, and therefore negative feedback is often included in the circuit. Subsequently we incorporate the Fourier transform/Poisson resummation method into a formalised and succinct analysis of a first-order negative feedback amplifier. Using perturbation expansions we derive the audio-frequency part of the output, demonstrating that negative feedback introduces undesirable distortion. Here we reveal the next order terms in the output compared with previous work, giving further insight into the nonlinear distortion. We then further extend the analysis to examine two more complex negative feedback topologies, namely a second-order and a derivative negative feedback design. Modelling each of these amplifiers presents an increased challenge due to the differences in their respective circuit designs, and in addition, for the derivative negative feedback amplifier we must consider scaling regimes based on the relative magnitudes of the frequencies involved. For both designs we establish novel expressions for the output, including the most significant distortion terms

Pulse time modulation for subcarrier multiplexed systems.

Subcarrier multiplexed (SCM) systems are an attractive alternative to the evolving digital technology for transmitting broadband services, at an affordable price. However, the majority of existing systems are based on analogue signal transmission and therefore, the strict noise and nonlinear requirements undermine the system performance. The work carried out in this thesis presents the feasibility of pulse time modulation (PTM), as a second stage modulator, in SCM systems.PTM techniques offer simplicity and low cost, and with the additional bandwidth available on optical fibres can trade bandwidth to significantly higher signal-to-noise ratio (SNR) levels, compared to analogue systems. Three different PTM techniques, square wave frequency modulation (SWFM), pulse frequency modulation (PFM) and pulse position modulation (PPM) has been investigated. A prototype system capable of transmitting a video channel, two audio channels and a data channel is implemented for each technique in order to evaluate the performance potential of PTM as a second stage modulator in SCM systems.The SNR expressions for all three schemes are derived from the first principles and the obtained results were verified experimentally. The optimum SNR performance is delivered by a raised cosine shaped pulse and the PPM technique delivers 5 dB SNR improvement over PFM. For SWFM systems a 3 dB SNR advantage is gained over single-edge detection technique and PFM systems by employing double-edge detection at the receiver. PPM spectrum contains a clock component which could be employed at the receiver for signal recovery. Demodulation technique, based on clock recovery using a phase locked loop (PLL) is proposed and implemented. This technique is cost effective and less complex compared to the existing demodulation schemes.The PFM implementation shows a 6 dB improvement in the receiver sensitivity compared to conventional SCM systems, while the PPM system offers an extra 2.5 dB improvement. The improved receiver sensitivity of the SCM-PTM technique, results in an increased optical power budget, where the transmission distance, number of subscribers and the number of channels in a network can be optimized. The nonlinear performance of the overall system is also shown to be within the specified performance levels

All-Digital High Resolution D/A Conversion by Dyadic Digital Pulse Modulation

In this paper, the limitations of digital-to-analog (D/A) conversion by Digital Pulse Width Modulation (DPWM) are addressed and the novel Dyadic Digital Pulse Modulation (DDPM) technique for all-digital, low cost, high resolution, Nyquist-rate D/A conversion is proposed. Thanks to the spectral characteristics of the new modulation, in particular, the requirements of the filter needed to extract the baseband component of DPWM signals can be significantly released so that to be suitable to inexpensive integration on silicon in analog interfaces for nanoscale integrated systems. After the new DDPM technique and its properties are introduced on a theoretical basis, the implementation of a D/A converter (DAC) based on the proposed modulation is addressed and its performance in terms of noise and linearity is discussed. A 16-bit DDPM-DAC prototype is finally synthesized on a field-programmable gate array (FPGA) and experimentally characterized

Cost-Effective and Energy-Efficient Techniques for Underwater Acoustic Communication Modems

Finally, the modem developed has been tested experimentally in laboratory (aquatic environment) showing that can communicates at different data rates (100..1200 bps) compared to state-of-the-art research modems. The software used include LabVIEW, MATLAB, Simulink, and Multisim (to test the electronic circuit built) has been employed.Underwater wireless sensor networks (UWSNs) are widely used in many applications related to ecosystem monitoring, and many more fields. Due to the absorption of electromagnetic waves in water and line-of-sight communication of optical waves, acoustic waves are the most suitable medium of communication in underwater environments. Underwater acoustic modem (UAM) is responsible for the transmission and reception of acoustic signals in an aquatic channel. Commercial modems may communicate at longer distances with reliability, but they are expensive and less power efficient. Research modems are designed by using a digital-signal-processor (DSP is expensive) and field-programmable-gate-array (FPGA is high power consuming device). In addition to, the use of a microcontroller is also a common practice (which is less expensive) but provides limited computational power. Hence, there is a need for a cost-effective and energy-efficient UAM to be used in budget limited applications. In this thesis different objectives are proposed. First, to identify the limitations of state-of-the-art commercial and research UAMs through a comprehensive survey. The second contribution has been the design of a low-cost acoustic modem for short-range underwater communications by using a single board computer (Raspberry-Pi), and a microcontroller (Atmega328P). The modulator, demodulator and amplifiers are designed with discrete components to reduce the overall cost. The third contribution is to design a web based underwater acoustic communication testbed along with a simulation platform (with underwater channel and sound propagation models), for testing modems. The fourth contribution is to integrate in a single module two important modules present in UAMs: the PSK modulator and the power amplifier